[PATCH 0/3] Misc ppc/e500 patches

[PATCH 0/3] Misc ppc/e500 patches

[BALATON Zoltan]

Some small patches to e500 related parts. Also includes a patch from
Bernhard that is rebased on current version.

Regards,
BALATON Zoltan

BALATON Zoltan (2):
  hw/ppc/e500: Move clock and TB frequency to machine class
  hw/net/fsl_etsec: Set default MAC address

Bernhard Beschow (1):
  hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal
    resources

 hw/net/fsl_etsec/etsec.c |  1 +
 hw/pci-host/ppce500.c    |  8 ++++----
 hw/ppc/e500.c            | 26 +++++++++++++-------------
 hw/ppc/e500.h            |  4 ++++
 hw/ppc/e500plat.c        |  2 ++
 hw/ppc/mpc8544ds.c       |  2 ++
 6 files changed, 26 insertions(+), 17 deletions(-)

-- 
2.41.3

[PATCH 1/3] hw/ppc/e500: Move clock and TB frequency to machine class

[BALATON Zoltan]

Different machines have different frequencies so make this
configurable in machine class instead of using a hard coded constant.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 hw/ppc/e500.c      | 18 +++++++++---------
 hw/ppc/e500.h      |  4 ++++
 hw/ppc/e500plat.c  |  2 ++
 hw/ppc/mpc8544ds.c |  2 ++
 4 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index 809078a2c3..dedd96b057 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -79,8 +79,6 @@
 #define MPC85XX_ESDHC_IRQ          72
 #define RTC_REGS_OFFSET            0x68
 
-#define PLATFORM_CLK_FREQ_HZ       (400 * 1000 * 1000)
-
 struct boot_info
 {
     uint32_t dt_base;
@@ -120,7 +118,7 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
 }
 
 static void dt_serial_create(void *fdt, unsigned long long offset,
-                             const char *soc, const char *mpic,
+                             const char *soc, uint32_t freq, const char *mpic,
                              const char *alias, int idx, bool defcon)
 {
     char *ser;
@@ -131,7 +129,7 @@ static void dt_serial_create(void *fdt, unsigned long long offset,
     qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
     qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
     qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
-    qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
+    qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq);
     qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
     qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
     qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
@@ -382,8 +380,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
     int fdt_size;
     void *fdt;
     uint8_t hypercall[16];
-    uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
-    uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
+    uint32_t clock_freq, tb_freq;
     int i;
     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
     char *soc;
@@ -484,6 +481,9 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
         if (kvmppc_get_hasidle(env)) {
             qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
         }
+    } else {
+        clock_freq = pmc->clock_freq;
+        tb_freq = pmc->tb_freq;
     }
 
     /* Create CPU nodes */
@@ -564,12 +564,12 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
      */
     if (serial_hd(1)) {
         dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
-                         soc, mpic, "serial1", 1, false);
+                         soc, pmc->clock_freq, mpic, "serial1", 1, false);
     }
 
     if (serial_hd(0)) {
         dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
-                         soc, mpic, "serial0", 0, true);
+                         soc, pmc->clock_freq, mpic, "serial0", 0, true);
     }
 
     /* i2c */
@@ -968,7 +968,7 @@ void ppce500_init(MachineState *machine)
         env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
         env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
 
-        ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
+        ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500);
 
         /* Register reset handler */
         if (!i) {
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 01db102625..00f490519c 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -5,6 +5,8 @@
 #include "hw/platform-bus.h"
 #include "qom/object.h"
 
+#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
+
 struct PPCE500MachineState {
     /*< private >*/
     MachineState parent_obj;
@@ -37,6 +39,8 @@ struct PPCE500MachineClass {
     hwaddr pci_mmio_base;
     hwaddr pci_mmio_bus_base;
     hwaddr spin_base;
+    uint32_t clock_freq;
+    uint32_t tb_freq;
 };
 
 void ppce500_init(MachineState *machine);
diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c
index 775b9d8da0..4f1d659e72 100644
--- a/hw/ppc/e500plat.c
+++ b/hw/ppc/e500plat.c
@@ -93,6 +93,8 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)
     pmc->pci_mmio_base = 0xC00000000ULL;
     pmc->pci_mmio_bus_base = 0xE0000000ULL;
     pmc->spin_base = 0xFEF000000ULL;
+    pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
+    pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
 
     mc->desc = "generic paravirt e500 platform";
     mc->init = e500plat_init;
diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c
index 97fb0f35ba..582698559d 100644
--- a/hw/ppc/mpc8544ds.c
+++ b/hw/ppc/mpc8544ds.c
@@ -55,6 +55,8 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)
     pmc->pci_mmio_bus_base = 0xC0000000ULL;
     pmc->pci_pio_base = 0xE1000000ULL;
     pmc->spin_base = 0xEF000000ULL;
+    pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
+    pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
 
     mc->desc = "mpc8544ds";
     mc->init = mpc8544ds_init;
-- 
2.41.3

[PATCH 2/3] hw/net/fsl_etsec: Set default MAC address

[BALATON Zoltan]

Use default MAC address if none is specified by property as done by
most other network interface models.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 hw/net/fsl_etsec/etsec.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
index d14cb2a101..846f6cbc5d 100644
--- a/hw/net/fsl_etsec/etsec.c
+++ b/hw/net/fsl_etsec/etsec.c
@@ -389,6 +389,7 @@ static void etsec_realize(DeviceState *dev, Error **errp)
 {
     eTSEC        *etsec = ETSEC_COMMON(dev);
 
+    qemu_macaddr_default_if_unset(&etsec->conf.macaddr);
     etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
                               object_get_typename(OBJECT(dev)), dev->id,
                               &dev->mem_reentrancy_guard, etsec);
-- 
2.41.3

[PATCH 3/3] hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources

[Bernhard Beschow]

From: Bernhard Beschow <shentey@gmail.com>

Rather than accessing the attributes of TYPE_CCSR directly, use the SysBusDevice
API which exists exactly for that purpose. Furthermore, registering the memory
region with the SysBusDevice API makes it show up in QMP's `info qom-tree`
command.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
[balaton: rebased]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
 hw/pci-host/ppce500.c | 8 ++++----
 hw/ppc/e500.c         | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
index e97a515d5f..52269b05bb 100644
--- a/hw/pci-host/ppce500.c
+++ b/hw/pci-host/ppce500.c
@@ -16,7 +16,6 @@
 
 #include "qemu/osdep.h"
 #include "hw/irq.h"
-#include "hw/ppc/e500-ccsr.h"
 #include "hw/qdev-properties.h"
 #include "migration/vmstate.h"
 #include "hw/pci/pci_device.h"
@@ -418,11 +417,12 @@ static const VMStateDescription vmstate_ppce500_pci = {
 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
 {
     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
-    PPCE500CCSRState *ccsr = CCSR(
+    SysBusDevice *ccsr = SYS_BUS_DEVICE(
         object_resolve_path_component(qdev_get_machine(), "e500-ccsr"));
+    MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0);
 
-    memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
-                             0, int128_get64(ccsr->ccsr_space.size));
+    memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
+                             ccsr_space, 0, int128_get64(ccsr_space->size));
     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
 }
 
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index dedd96b057..6899802bed 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -931,7 +931,6 @@ void ppce500_init(MachineState *machine)
     CPUPPCState *firstenv = NULL;
     MemoryRegion *ccsr_addr_space;
     SysBusDevice *s;
-    PPCE500CCSRState *ccsr;
     I2CBus *i2c;
 
     irqs = g_new0(IrqLines, smp_cpus);
@@ -993,10 +992,10 @@ void ppce500_init(MachineState *machine)
     memory_region_add_subregion(address_space_mem, 0, machine->ram);
 
     dev = qdev_new("e500-ccsr");
+    s = SYS_BUS_DEVICE(dev);
     object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-    ccsr = CCSR(dev);
-    ccsr_addr_space = &ccsr->ccsr_space;
+    sysbus_realize_and_unref(s, &error_fatal);
+    ccsr_addr_space = sysbus_mmio_get_region(s, 0);
     memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
                                 ccsr_addr_space);
 
@@ -1284,6 +1283,7 @@ static void e500_ccsr_initfn(Object *obj)
     PPCE500CCSRState *ccsr = CCSR(obj);
     memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
                        MPC8544_CCSRBAR_SIZE);
+    sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space);
 }
 
 static const TypeInfo e500_ccsr_info = {
-- 
2.41.3

Re: [PATCH 3/3] hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources

[BALATON Zoltan]

On Fri, 23 May 2025, Bernhard Beschow wrote:
> From: Bernhard Beschow <shentey@gmail.com>

This was meant to be only here but somehow it alse overwrote the ream 
From that should have been my address. Sorry for that, but patch is still 
correct.

Regards,
BALATON Zoltan

> Rather than accessing the attributes of TYPE_CCSR directly, use the SysBusDevice
> API which exists exactly for that purpose. Furthermore, registering the memory
> region with the SysBusDevice API makes it show up in QMP's `info qom-tree`
> command.
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
> [balaton: rebased]
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/pci-host/ppce500.c | 8 ++++----
> hw/ppc/e500.c         | 8 ++++----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c
> index e97a515d5f..52269b05bb 100644
> --- a/hw/pci-host/ppce500.c
> +++ b/hw/pci-host/ppce500.c
> @@ -16,7 +16,6 @@
>
> #include "qemu/osdep.h"
> #include "hw/irq.h"
> -#include "hw/ppc/e500-ccsr.h"
> #include "hw/qdev-properties.h"
> #include "migration/vmstate.h"
> #include "hw/pci/pci_device.h"
> @@ -418,11 +417,12 @@ static const VMStateDescription vmstate_ppce500_pci = {
> static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
> {
>     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
> -    PPCE500CCSRState *ccsr = CCSR(
> +    SysBusDevice *ccsr = SYS_BUS_DEVICE(
>         object_resolve_path_component(qdev_get_machine(), "e500-ccsr"));
> +    MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0);
>
> -    memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
> -                             0, int128_get64(ccsr->ccsr_space.size));
> +    memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
> +                             ccsr_space, 0, int128_get64(ccsr_space->size));
>     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
> }
>
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index dedd96b057..6899802bed 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -931,7 +931,6 @@ void ppce500_init(MachineState *machine)
>     CPUPPCState *firstenv = NULL;
>     MemoryRegion *ccsr_addr_space;
>     SysBusDevice *s;
> -    PPCE500CCSRState *ccsr;
>     I2CBus *i2c;
>
>     irqs = g_new0(IrqLines, smp_cpus);
> @@ -993,10 +992,10 @@ void ppce500_init(MachineState *machine)
>     memory_region_add_subregion(address_space_mem, 0, machine->ram);
>
>     dev = qdev_new("e500-ccsr");
> +    s = SYS_BUS_DEVICE(dev);
>     object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
> -    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> -    ccsr = CCSR(dev);
> -    ccsr_addr_space = &ccsr->ccsr_space;
> +    sysbus_realize_and_unref(s, &error_fatal);
> +    ccsr_addr_space = sysbus_mmio_get_region(s, 0);
>     memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
>                                 ccsr_addr_space);
>
> @@ -1284,6 +1283,7 @@ static void e500_ccsr_initfn(Object *obj)
>     PPCE500CCSRState *ccsr = CCSR(obj);
>     memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
>                        MPC8544_CCSRBAR_SIZE);
> +    sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space);
> }
>
> static const TypeInfo e500_ccsr_info = {
>

Re: [PATCH 2/3] hw/net/fsl_etsec: Set default MAC address

[Bernhard Beschow]

Am 23. Mai 2025 15:02:12 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>Use default MAC address if none is specified by property as done by
>most other network interface models.
>
>Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>---
> hw/net/fsl_etsec/etsec.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c
>index d14cb2a101..846f6cbc5d 100644
>--- a/hw/net/fsl_etsec/etsec.c
>+++ b/hw/net/fsl_etsec/etsec.c
>@@ -389,6 +389,7 @@ static void etsec_realize(DeviceState *dev, Error **errp)
> {
>     eTSEC        *etsec = ETSEC_COMMON(dev);
> 
>+    qemu_macaddr_default_if_unset(&etsec->conf.macaddr);
>     etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
>                               object_get_typename(OBJECT(dev)), dev->id,
>                               &dev->mem_reentrancy_guard, etsec);

Reviewed-by: Bernhard Beschow <shentey@gmail.com>

Re: [PATCH 0/3] Misc ppc/e500 patches

[Bernhard Beschow]

Am 23. Mai 2025 15:02:10 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>Some small patches to e500 related parts. Also includes a patch from
>Bernhard that is rebased on current version.
>
>Regards,
>BALATON Zoltan
>
>BALATON Zoltan (2):
>  hw/ppc/e500: Move clock and TB frequency to machine class
>  hw/net/fsl_etsec: Set default MAC address
>
>Bernhard Beschow (1):
>  hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal
>    resources
>
> hw/net/fsl_etsec/etsec.c |  1 +
> hw/pci-host/ppce500.c    |  8 ++++----
> hw/ppc/e500.c            | 26 +++++++++++++-------------
> hw/ppc/e500.h            |  4 ++++
> hw/ppc/e500plat.c        |  2 ++
> hw/ppc/mpc8544ds.c       |  2 ++
> 6 files changed, 26 insertions(+), 17 deletions(-)
>

Series:
Acked-by: Bernhard Beschow <shentey@gmail.com>