From: Tao Ding <dingtao0430@163.com>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Tao Ding <dingtao0430@163.com>
Subject: [PATCH v1 0/3] Fixed bugs in pl080
Date: Thu, 12 Mar 2026 16:02:32 +0800 [thread overview]
Message-ID: <cover.1773301927.git.dingtao0430@163.com> (raw)
Hi all,
When I tested pl080 using the existing dmatest tool in Linux,
I found that pl080 could not output the results correctly.
The main issues involved are inconsistent source and destination bit widths,
misalignment of LLI, which can lead to incorrect data and even cause qemu crashes.
Tao Ding (3):
An interrupt is generated after the DMA transfer complete.
The swidth and dwidth of pl080 are not equal.
The LLI of pl080 should be aligned with 4 bytes.
hw/dma/pl080.c | 45 ++++++++++++++++++++++++++++-----------------
1 file changed, 28 insertions(+), 17 deletions(-)
base-commit: 1fd5ff9d76d23ab23a68419cbc76d5ee33e8b455
--
2.43.0
next reply other threads:[~2026-03-12 13:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-12 8:02 Tao Ding [this message]
2026-03-12 8:02 ` [PATCH v1 1/3] An interrupt is generated after the DMA transfer complete Tao Ding
2026-03-12 8:02 ` [PATCH v1 2/3] The swidth and dwidth of pl080 are not equal Tao Ding
2026-03-13 12:20 ` Peter Maydell
2026-03-14 17:14 ` Tao Ding
2026-03-23 16:50 ` [PATCH v2 0/1] Fix transfer size register decrement Tao Ding
2026-03-23 16:50 ` [PATCH v2 1/1] Fix transfer size register decrement in pl080 Tao Ding
2026-03-24 12:01 ` Peter Maydell
2026-03-12 8:02 ` [PATCH v1 3/3] The LLI of pl080 should be aligned with 4 bytes Tao Ding
2026-03-13 11:26 ` Peter Maydell
2026-03-13 12:35 ` [PATCH v1 0/3] Fixed bugs in pl080 Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2026-03-11 14:24 1774596582
2026-03-11 16:14 ` Tao Tang
2026-03-11 17:05 ` Peter Maydell
2026-03-11 18:04 ` 有点
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