From: Fengyuan Yu <15fengyuan@gmail.com>
To: "Tao Tang" <tangtao1634@phytium.com.cn>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Jason Wang" <jasowang@redhat.com>, "Yi Liu" <yi.l.liu@intel.com>,
"Clément Mathieu--Drif" <clement.mathieu--drif@bull.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Zhao Liu" <zhao1.liu@intel.com>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>
Cc: qemu-devel@nongnu.org, Chao Liu <chao.liu.zevorn@gmail.com>,
Fengyuan Yu <15fengyuan@gmail.com>
Subject: [PATCH v2 0/2] tests/qtest: Add Intel IOMMU bare-metal test using iommu-testdev
Date: Sat, 14 Mar 2026 09:11:35 +0800 [thread overview]
Message-ID: <cover.1773450180.git.15fengyuan@gmail.com> (raw)
Hi,
This patch series adds a bare-metal qtest for the Intel IOMMU (VT-d) using
the iommu-testdev framework. The test exercises address translation paths
without requiring a full guest OS boot.
Motivation
----------
The Intel IOMMU implementation in QEMU supports various translation
modes. Currently, comprehensive testing of these translation paths
requires booting a full guest OS with appropriate drivers, which is
time-consuming and makes regression testing difficult.
This new test fills that gap by using iommu-testdev to trigger DMA
transactions and validate the IOMMU's translation logic directly.
Test Coverage
-------------
The new test provides:
- Legacy pass-through mode (identity mapping)
- Legacy translated mode with 4-level second-level page table walks
- Scalable pass-through mode (PGTT=100b)
- Scalable second-level translation mode (PGTT=010b)
- Scalable first-level translation mode (PGTT=001b)
- Root/Context Entry, PASID Directory/Table Entry configuration
- Complete 48-bit address space translation
- End-to-end DMA verification with memory validation
Testing
-------
QTEST_QEMU_BINARY=./build/qemu-system-x86_64 \
./build/tests/qtest/iommu-intel-test --tap -k
Changes v1 -> v2
----------------
- Rebase onto latest upstream to resolve compilation errors
- Add scalable translation mode tests (SLT, FLT, PassThrough)
- Add spec-aligned register field comments for improved readability
Thanks,
Fengyuan
Fengyuan Yu (2):
tests/qtest/libqos: Add Intel IOMMU helper library
tests/qtest: Add Intel IOMMU bare-metal test
MAINTAINERS | 6 +
tests/qtest/iommu-intel-test.c | 215 +++++++++++++
tests/qtest/libqos/meson.build | 3 +
tests/qtest/libqos/qos-intel-iommu.c | 454 +++++++++++++++++++++++++++
tests/qtest/libqos/qos-intel-iommu.h | 191 +++++++++++
tests/qtest/meson.build | 2 +
6 files changed, 871 insertions(+)
create mode 100644 tests/qtest/iommu-intel-test.c
create mode 100644 tests/qtest/libqos/qos-intel-iommu.c
create mode 100644 tests/qtest/libqos/qos-intel-iommu.h
--
2.39.5
next reply other threads:[~2026-03-14 1:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-14 1:11 Fengyuan Yu [this message]
2026-03-14 1:11 ` [PATCH v2 1/2] tests/qtest/libqos: Add Intel IOMMU helper library Fengyuan Yu
2026-03-17 1:38 ` Chao Liu
2026-03-24 3:33 ` Tao Tang
2026-03-24 23:53 ` Fengyuan
2026-03-24 4:12 ` Tao Tang
2026-03-24 23:50 ` Fengyuan
2026-03-14 1:11 ` [PATCH v2 2/2] tests/qtest: Add Intel IOMMU bare-metal test Fengyuan Yu
2026-03-17 11:15 ` Chao Liu
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