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[2001:8b0:bb71:7140:64::1]) by smtp.gmail.com with ESMTPSA id 67sm2035162wmz.46.2021.02.02.01.46.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 01:46:56 -0800 (PST) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 8d11781d; Tue, 2 Feb 2021 09:46:55 +0000 (UTC) To: =?utf-8?Q?Daniel_P=2E_Berrang=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH RFC 2/4] target/i386: define CPU models to model x86-64 ABI levels In-Reply-To: <20210201153606.4158076-3-berrange@redhat.com> References: <20210201153606.4158076-1-berrange@redhat.com> <20210201153606.4158076-3-berrange@redhat.com> X-HGTTG: zarquon From: David Edmondson X-Now-Playing: Peter Gabriel - Up: Sky Blue Date: Tue, 02 Feb 2021 09:46:55 +0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: neutral client-ip=2a00:1450:4864:20::335; envelope-from=dme@dme.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Weimer , =?utf-8?Q?Daniel_P=2E_Berrang?= =?utf-8?Q?=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Monday, 2021-02-01 at 15:36:04 GMT, Daniel P. Berrang=C3=A9 wrote: > To paraphrase: > > https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterpri= se-linux-9-for-the-x86-64-v2-microarchitecture-level/ > > In 2020, AMD, Intel, Red Hat, and SUSE worked together to define > three microarchitecture levels on top of the historical x86-64 > baseline: > > * x86-64: original x86_64 baseline instruction set > * x86-64-v2: vector instructions up to Streaming SIMD > Extensions 4.2 (SSE4.2) and Supplemental > Streaming SIMD Extensions 3 (SSSE3), the > POPCNT instruction, and CMPXCHG16B > * x86-64-v3: vector instructions up to AVX2, MOVBE, > and additional bit-manipulation instructions. > * x86-64-v4: vector instructions from some of the > AVX-512 variants. > > This list of features is defined in the doc at: > > https://gitlab.com/x86-psABIs/x86-64-ABI/ > > QEMU has historically defaulted to the "qemu64" CPU model on > x86_64 targets, which is approximately the x86-64 baseline > ABI, with 'SVM' added. > > It is thought it might be desirable if QEMU could provide CPU models > that closely correspond to the ABI levels, while offering portability > across the maximum number of physical CPUs. > > Historically we've found that defining CPU models with an arbitrary > combination of CPU features can be problematic, as some guest OS > will not check all features they use, and instead assume that if > they see feature "XX", then "YY" will always exist. This is reasonable > in bare metal, but subject to breakage in virtualization. > > Thus in defining the CPI models for the ABI levels, this patch attempted s/CPI/CPU/ > to base them off an existing CPU model. > > While each x86-64-abiNNN has a designated vendor, they are designed > to be vendor agnostic models. ie they are capable of running on any > AMD or Intel physical CPU model that satisfies the ABI level. eg Only AMD or Intel? (You mention the Hugon chips elsewhere.) > althgouh the x86-64-abi2 model is based on Nehalem, it should be > able to run guests on an Opteron_G4/G5/EPYC host, since those CPUs > support the features required by the x86-64 v2 ABI. > > More precisely the models were defined as: > > * x86-64-abi1: close match for Opteron_G1, minus > vme > * x86-64-abi2: perfect match for Nehalem > * x86-64-abi3: close match of Haswell-noTSX, minus > aes pcid erms invpcid tsc-deadline > x2apic pclmulqdq > * x86-64-abi4: close match of Skylake-Server-noTSX-IBRS, minus > spec-ctrl > > None of the CPU models declare any VMX/SVM features. This would > make them unable to support nested virtualization with live > migration. How about "Unable to support hardware accelerated nested virtualization." ? Is live migration relevant? > Given their vendor agnostic design, these CPU models are primarily > though to useful as the default CPU model for machine types. QEMU > upstream is quite conservative in mandating new hardware features, > but a downstream vendor may choose to mandate a newer x86-64 ABI > level for downstream only machine types. > > Note that TCG is not capable of supporting the 2 newest ABI levels > currently: > > * x86-64-abi3: > > CPUID.01H:ECX.fma [bit 12] > CPUID.01H:ECX.avx [bit 28] > CPUID.01H:ECX.f16c [bit 29] > CPUID.07H:EBX.avx2 [bit 5] > > * x86-64-abi4: > > CPUID.01H:ECX.pcid [bit 17] > CPUID.01H:ECX.x2apic [bit 21] > CPUID.01H:ECX.tsc-deadline [bit 24] > CPUID.07H:EBX.invpcid [bit 10] > CPUID.07H:EBX.avx512f [bit 16] > CPUID.07H:EBX.avx512dq [bit 17] > CPUID.07H:EBX.rdseed [bit 18] > CPUID.07H:EBX.avx512cd [bit 28] > CPUID.07H:EBX.avx512bw [bit 30] > CPUID.07H:EBX.avx512vl [bit 31] > CPUID.80000001H:ECX.3dnowprefetch [bit 8] > CPUID.0DH:EAX.xsavec [bit 1] > > Signed-off-by: Daniel P. Berrang=C3=A9 > --- > docs/system/cpu-models-x86-abi.csv | 8 ++ > target/i386/cpu.c | 156 +++++++++++++++++++++++++++++ > 2 files changed, 164 insertions(+) > > diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-= x86-abi.csv > index 4565e6a535..d34d95d485 100644 > --- a/docs/system/cpu-models-x86-abi.csv > +++ b/docs/system/cpu-models-x86-abi.csv > @@ -119,3 +119,11 @@ qemu32,,,, > qemu32-v1,,,, > qemu64,=E2=9C=85,,, > qemu64-v1,=E2=9C=85,,, > +x86-64-abi1,=E2=9C=85,,, > +x86-64-abi1-v1,=E2=9C=85,,, > +x86-64-abi2,=E2=9C=85,=E2=9C=85,, > +x86-64-abi2-v1,=E2=9C=85,=E2=9C=85,, > +x86-64-abi3,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +x86-64-abi3-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +x86-64-abi4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +x86-64-abi4-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index ae89024d36..87a775a5eb 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1827,6 +1827,162 @@ static CPUCaches epyc_rome_cache_info =3D { > */ >=20=20 > static X86CPUDefinition builtin_x86_defs[] =3D { > + /* > + * These first few CPU models are designed to satisfy the > + * x86_64 ABI levels defined in: > + * > + * https://gitlab.com/x86-psABIs/x86-64-ABI/ > + * > + * They were constructed as follows: > + * > + * - Find all the CPU models which can satisfy the ABI > + * - Calculate the lowest common denominator (LCD) of these > + * models' features > + * - Find the named model most closely matching the LCD > + * - Strip its features back to the LCD > + * > + * The above spec uses the "x86-64-vNN" naming convention. > + * This clashes with the "vNN" suffix QEMU uses for versioning. > + * Thus we use "abiNNN" as a suffix. > + */ > + { > + /* > + * Derived from Opteron_G1, minus > + * vme > + */ > + .name =3D "x86-64-abi1", > + .level =3D 5, > + .vendor =3D CPUID_VENDOR_AMD, > + .family =3D 15, > + .model =3D 6, > + .stepping =3D 1, > + .features[FEAT_1_EDX] =3D > + CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID= _MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] =3D > + CPUID_EXT_SSE3, > + .features[FEAT_8000_0001_EDX] =3D > + CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, > + .xlevel =3D 0x80000008, > + .model_id =3D "QEMU x86-64 baseline ABI", > + }, > + { > + /* Derived from Nehalem */ > + .name =3D "x86-64-abi2", > + .level =3D 11, > + .vendor =3D CPUID_VENDOR_INTEL, > + .family =3D 6, > + .model =3D 26, > + .stepping =3D 3, > + .features[FEAT_1_EDX] =3D > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID= _MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] =3D > + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | > + CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, > + .features[FEAT_8000_0001_EDX] =3D > + CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, > + .features[FEAT_8000_0001_ECX] =3D > + CPUID_EXT3_LAHF_LM, > + .xlevel =3D 0x80000008, > + .model_id =3D "QEMU x86-64-v2 ABI", > + }, > + { > + /* > + * Derived from Haswell-noTSX, minus > + * aes pcid erms invpcid tsc-deadline x2apic pclmulqdq > + */ > + .name =3D "x86-64-abi3", > + .level =3D 0xd, > + .vendor =3D CPUID_VENDOR_INTEL, > + .family =3D 6, > + .model =3D 60, > + .stepping =3D 1, > + .features[FEAT_1_EDX] =3D > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID= _MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] =3D > + CPUID_EXT_AVX | CPUID_EXT_XSAVE | > + CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | > + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > + CPUID_EXT_SSE3 | > + CPUID_EXT_FMA | CPUID_EXT_MOVBE | > + CPUID_EXT_F16C | CPUID_EXT_RDRAND, > + .features[FEAT_8000_0001_EDX] =3D > + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | > + CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] =3D > + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, > + .features[FEAT_7_0_EBX] =3D > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_BMI2, > + .features[FEAT_XSAVE] =3D > + CPUID_XSAVE_XSAVEOPT, > + .features[FEAT_6_EAX] =3D > + CPUID_6_EAX_ARAT, > + .xlevel =3D 0x80000008, > + .model_id =3D "QEMU x86-64-v3 ABI", > + }, > + > + { > + /* > + * Derived from Skylake-Server-noTSX-IBRS, minus: > + * spec-ctrl > + */ > + .name =3D "x86-64-abi4", > + .level =3D 0xd, > + .vendor =3D CPUID_VENDOR_INTEL, > + .family =3D 6, > + .model =3D 85, > + .stepping =3D 4, > + .features[FEAT_1_EDX] =3D > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID= _MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] =3D > + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | > + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | > + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOV= BE | > + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, > + .features[FEAT_8000_0001_EDX] =3D > + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | > + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] =3D > + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFET= CH, > + .features[FEAT_7_0_EBX] =3D > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > + CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVP= CID | > + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > + CPUID_7_0_EBX_AVX512VL, > + .features[FEAT_7_0_ECX] =3D > + CPUID_7_0_ECX_PKU, > + .features[FEAT_XSAVE] =3D > + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | > + CPUID_XSAVE_XGETBV1, > + .features[FEAT_6_EAX] =3D > + CPUID_6_EAX_ARAT, > + .xlevel =3D 0x80000008, > + .model_id =3D "QEMU x86-64-v4 ABI", > + }, > + > { > .name =3D "qemu64", > .level =3D 0xd, > --=20 > 2.29.2 dme. --=20 All those lines and circles, to me, a mystery.