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[2001:8b0:bb71:7140:64::1]) by smtp.gmail.com with ESMTPSA id v13sm1676132wrd.51.2021.02.02.01.41.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Feb 2021 01:41:16 -0800 (PST) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 93ba75a0; Tue, 2 Feb 2021 09:41:15 +0000 (UTC) To: =?utf-8?Q?Daniel_P=2E_Berrang=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH RFC 1/4] docs: add a table showing x86-64 ABI compatibility levels In-Reply-To: <20210201153606.4158076-2-berrange@redhat.com> References: <20210201153606.4158076-1-berrange@redhat.com> <20210201153606.4158076-2-berrange@redhat.com> X-HGTTG: zarquon From: David Edmondson X-Now-Playing: Peter Gabriel - Up: Sky Blue Date: Tue, 02 Feb 2021 09:41:15 +0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: neutral client-ip=2a00:1450:4864:20::42c; envelope-from=dme@dme.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NEUTRAL=0.779, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Florian Weimer , =?utf-8?Q?Daniel_P=2E_Berrang?= =?utf-8?Q?=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Monday, 2021-02-01 at 15:36:03 GMT, Daniel P. Berrang=C3=A9 wrote: > It is useful to know which CPUs satisfy each x86-64 ABI > compatibility level, when dealing with guest OS that require > something newer than the baseline ABI. > > These ABI levels are defined in: > > https://gitlab.com/x86-psABIs/x86-64-ABI/ > > and supported by GCC, CLang, GLibC and more. > > Signed-off-by: Daniel P. Berrang=C3=A9 > --- > MAINTAINERS | 2 +- > docs/system/cpu-models-x86-abi.csv | 121 +++++++++++++++++++++++++++++ > docs/system/cpu-models-x86.rst.inc | 18 +++++ > 3 files changed, 140 insertions(+), 1 deletion(-) > create mode 100644 docs/system/cpu-models-x86-abi.csv > > diff --git a/MAINTAINERS b/MAINTAINERS > index fbb228ef2b..bb8d60c458 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -344,7 +344,7 @@ F: tests/tcg/i386/ > F: tests/tcg/x86_64/ > F: hw/i386/ > F: disas/i386.c > -F: docs/system/cpu-models-x86.rst.inc > +F: docs/system/cpu-models-x86* > T: git https://gitlab.com/ehabkost/qemu.git x86-next >=20=20 > Xtensa TCG CPUs > diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-= x86-abi.csv > new file mode 100644 > index 0000000000..4565e6a535 > --- /dev/null > +++ b/docs/system/cpu-models-x86-abi.csv > @@ -0,0 +1,121 @@ > +Model,baseline,v2,v3,v4 > +486,,,, > +486-v1,,,, > +Broadwell,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-noTSX,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-noTSX-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, Would it be useful to add an explicit negative mark (=E2=9C=98) in the slots where the CPU does not satisfy the requirement? It makes reading the table a little easier (my opinion, of course). > +Broadwell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Broadwell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Cascadelake-Server,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cascadelake-Server-noTSX,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cascadelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cascadelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cascadelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cascadelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Conroe,=E2=9C=85,,, > +Conroe-v1,=E2=9C=85,,, > +Cooperlake,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Cooperlake-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Denverton,=E2=9C=85,=E2=9C=85,, > +Denverton-v1,=E2=9C=85,=E2=9C=85,, > +Denverton-v2,=E2=9C=85,=E2=9C=85,, > +Dhyana,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Dhyana-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-IBPB,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-Rome,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-Rome-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +EPYC-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-noTSX,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-noTSX-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Haswell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Icelake-Client,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Icelake-Client-noTSX,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Icelake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Icelake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Icelake-Server,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Icelake-Server-noTSX,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Icelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Icelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Icelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Icelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +IvyBridge,=E2=9C=85,=E2=9C=85,, > +IvyBridge-IBRS,=E2=9C=85,=E2=9C=85,, > +IvyBridge-v1,=E2=9C=85,=E2=9C=85,, > +IvyBridge-v2,=E2=9C=85,=E2=9C=85,, > +KnightsMill,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +KnightsMill-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Nehalem,=E2=9C=85,=E2=9C=85,, > +Nehalem-IBRS,=E2=9C=85,=E2=9C=85,, > +Nehalem-v1,=E2=9C=85,=E2=9C=85,, > +Nehalem-v2,=E2=9C=85,=E2=9C=85,, > +Opteron_G1,=E2=9C=85,,, > +Opteron_G1-v1,=E2=9C=85,,, > +Opteron_G2,=E2=9C=85,,, > +Opteron_G2-v1,=E2=9C=85,,, > +Opteron_G3,=E2=9C=85,,, > +Opteron_G3-v1,=E2=9C=85,,, > +Opteron_G4,=E2=9C=85,=E2=9C=85,, > +Opteron_G4-v1,=E2=9C=85,=E2=9C=85,, > +Opteron_G5,=E2=9C=85,=E2=9C=85,, > +Opteron_G5-v1,=E2=9C=85,=E2=9C=85,, > +Penryn,=E2=9C=85,,, > +Penryn-v1,=E2=9C=85,,, > +SandyBridge,=E2=9C=85,=E2=9C=85,, > +SandyBridge-IBRS,=E2=9C=85,=E2=9C=85,, > +SandyBridge-v1,=E2=9C=85,=E2=9C=85,, > +SandyBridge-v2,=E2=9C=85,=E2=9C=85,, > +Skylake-Client,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Client-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Client-noTSX-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Client-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, > +Skylake-Server,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-noTSX-IBRS,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Skylake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 > +Snowridge,=E2=9C=85,=E2=9C=85,, > +Snowridge-v1,=E2=9C=85,=E2=9C=85,, > +Snowridge-v2,=E2=9C=85,=E2=9C=85,, > +Westmere,=E2=9C=85,=E2=9C=85,, > +Westmere-IBRS,=E2=9C=85,=E2=9C=85,, > +Westmere-v1,=E2=9C=85,=E2=9C=85,, > +Westmere-v2,=E2=9C=85,=E2=9C=85,, > +athlon,,,, > +athlon-v1,,,, > +core2duo,=E2=9C=85,,, > +core2duo-v1,=E2=9C=85,,, > +coreduo,,,, > +coreduo-v1,,,, > +kvm32,,,, > +kvm32-v1,,,, > +kvm64,=E2=9C=85,,, > +kvm64-v1,=E2=9C=85,,, > +n270,,,, > +n270-v1,,,, > +pentium,,,, > +pentium-v1,,,, > +pentium2,,,, > +pentium2-v1,,,, > +pentium3,,,, > +pentium3-v1,,,, > +phenom,=E2=9C=85,,, > +phenom-v1,=E2=9C=85,,, > +qemu32,,,, > +qemu32-v1,,,, > +qemu64,=E2=9C=85,,, > +qemu64-v1,=E2=9C=85,,, > diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-= x86.rst.inc > index 9a2327828e..b964b29c78 100644 > --- a/docs/system/cpu-models-x86.rst.inc > +++ b/docs/system/cpu-models-x86.rst.inc > @@ -39,6 +39,24 @@ CPU, as they would with "Host passthrough", but gives = much of the > benefit of passthrough, while making live migration safe. >=20=20 >=20=20 > +ABI compatibility levels for CPU models > +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > + > +The x86_64 architecture has a number of `ABI compatibility levels`_ > +defined. Traditionally most operating systems and toolchains would > +only target the original baseline ABI. It is expected that in > +future OS and toolchains are likely to target newer ABIs. The > +following table illustrates which ABI compatibility levels can be > +satisfied by the QEMU CPU models Missing full stop (or colon?). > + > +.. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/ > + > +.. csv-table:: x86-64 ABI compatibility levels > + :file: cpu-models-x86-abi.csv > + :widths: 40,15,15,15,15 > + :header-rows: 1 > + > + > Preferred CPU models for Intel x86 hosts > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ >=20=20 > --=20 > 2.29.2 dme. --=20 All of us, we're going out tonight. We're gonna walk all over your cars.