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[174.21.74.48]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-225c6bbe5a2sm116503485ad.196.2025.03.19.09.08.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Mar 2025 09:08:32 -0700 (PDT) Message-ID: Date: Wed, 19 Mar 2025 09:08:31 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-10.1 01/12] tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h' To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: Anton Johansson , Peter Maydell , Pierrick Bouvier References: <20250319134507.45045-1-philmd@linaro.org> <20250319134507.45045-2-philmd@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250319134507.45045-2-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/19/25 06:44, Philippe Mathieu-Daudé wrote: > To avoid including the huge "cpu.h" for a simple definition, > move TARGET_INSN_START_EXTRA_WORDS to "cpu-param.h". > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/arm/cpu-param.h | 14 ++++++++++++++ > target/arm/cpu.h | 14 -------------- > target/hppa/cpu-param.h | 2 ++ > target/hppa/cpu.h | 2 -- > target/i386/cpu-param.h | 2 ++ > target/i386/cpu.h | 2 -- > target/m68k/cpu-param.h | 2 ++ > target/m68k/cpu.h | 2 -- > target/microblaze/cpu-param.h | 2 ++ > target/microblaze/cpu.h | 2 -- > target/mips/cpu-param.h | 2 ++ > target/mips/cpu.h | 2 -- > target/openrisc/cpu-param.h | 2 ++ > target/openrisc/cpu.h | 2 -- > target/riscv/cpu-param.h | 8 ++++++++ > target/riscv/cpu.h | 6 ------ > target/s390x/cpu-param.h | 2 ++ > target/s390x/cpu.h | 2 -- > target/sh4/cpu-param.h | 2 ++ > target/sh4/cpu.h | 2 -- > target/sparc/cpu-param.h | 2 ++ > target/sparc/cpu.h | 1 - > 22 files changed, 40 insertions(+), 37 deletions(-) > > diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h > index 896b35bd6d5..ed1f0b16e51 100644 > --- a/target/arm/cpu-param.h > +++ b/target/arm/cpu-param.h > @@ -38,6 +38,20 @@ > # define TARGET_PAGE_BITS_MIN 10 > #endif /* !CONFIG_USER_ONLY */ > > +/* ARM-specific extra insn start words: > + * 1: Conditional execution bits > + * 2: Partial exception syndrome for data aborts > + */ > +#define TARGET_INSN_START_EXTRA_WORDS 2 > + > +/* The 2nd extra word holding syndrome info for data aborts does not use > + * the upper 6 bits nor the lower 13 bits. We mask and shift it down to > + * help the sleb128 encoder do a better job. > + * When restoring the CPU state, we shift it back up. > + */ > +#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1) > +#define ARM_INSN_START_WORD2_SHIFT 13 This does not belong in cpu-param.h. This is private to target/arm/, and should probably be moved to internals.h or translate.h or some such. Otherwise, Reviewed-by: Richard Henderson r~