* [PATCH v2 01/11] readline: fix hmp completion issue
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 02/11] hw/i2c: only schedule pending master when bus is idle Cédric Le Goater
` (9 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery, Dongli Zhang,
Joe Jin, Thomas Huth, Markus Armbruster,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Dongli Zhang <dongli.zhang@oracle.com>
The auto completion does not work in some cases.
Case 1.
1. (qemu) info reg
2. Press 'Tab'.
3. It does not auto complete.
Case 2.
1. (qemu) block_resize flo
2. Press 'Tab'.
3. It does not auto complete 'floppy0'.
Since the readline_add_completion_of() may add any completion when
strlen(pfx) is zero, we remove the check with (name[0] == '\0') because
strlen() always returns zero in that case.
Fixes: 52f50b1e9f8f ("readline: Extract readline_add_completion_of() from monitor")
Cc: Joe Jin <joe.jin@oracle.com>
Signed-off-by: Dongli Zhang <dongli.zhang@oracle.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
monitor/hmp.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/monitor/hmp.c b/monitor/hmp.c
index 2aa85d3982..fee410362f 100644
--- a/monitor/hmp.c
+++ b/monitor/hmp.c
@@ -1189,9 +1189,7 @@ static void cmd_completion(MonitorHMP *mon, const char *name, const char *list)
}
memcpy(cmd, pstart, len);
cmd[len] = '\0';
- if (name[0] == '\0') {
- readline_add_completion_of(mon->rs, name, cmd);
- }
+ readline_add_completion_of(mon->rs, name, cmd);
if (*p == '\0') {
break;
}
@@ -1335,9 +1333,7 @@ static void monitor_find_completion_by_table(MonitorHMP *mon,
/* block device name completion */
readline_set_completion_index(mon->rs, strlen(str));
while ((blk = blk_next(blk)) != NULL) {
- if (str[0] == '\0') {
- readline_add_completion_of(mon->rs, str, blk_name(blk));
- }
+ readline_add_completion_of(mon->rs, str, blk_name(blk));
}
break;
case 's':
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 02/11] hw/i2c: only schedule pending master when bus is idle
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 01/11] readline: fix hmp completion issue Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 03/11] hw/misc: add a toy i2c echo device Cédric Le Goater
` (8 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery, Klaus Jensen,
Corey Minyard, Cédric Le Goater
From: Klaus Jensen <k.jensen@samsung.com>
It is not given that the current master will release the bus after a
transfer ends. Only schedule a pending master if the bus is idle.
Fixes: 37fa5ca42623 ("hw/i2c: support multiple masters")
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Message-Id: <20221116084312.35808-2-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/i2c/i2c.h | 2 ++
hw/i2c/aspeed_i2c.c | 2 ++
hw/i2c/core.c | 37 ++++++++++++++++++++++---------------
3 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
index 9b9581d230..2a3abacd1b 100644
--- a/include/hw/i2c/i2c.h
+++ b/include/hw/i2c/i2c.h
@@ -141,6 +141,8 @@ int i2c_start_send(I2CBus *bus, uint8_t address);
*/
int i2c_start_send_async(I2CBus *bus, uint8_t address);
+void i2c_schedule_pending_master(I2CBus *bus);
+
void i2c_end_transfer(I2CBus *bus);
void i2c_nack(I2CBus *bus);
void i2c_ack(I2CBus *bus);
diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index c166fd20fa..1f071a3811 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -550,6 +550,8 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value)
}
SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_STOP_CMD, 0);
aspeed_i2c_set_state(bus, I2CD_IDLE);
+
+ i2c_schedule_pending_master(bus->bus);
}
if (aspeed_i2c_bus_pkt_mode_en(bus)) {
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index d4ba8146bf..bed594fe59 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -185,22 +185,39 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv)
void i2c_bus_master(I2CBus *bus, QEMUBH *bh)
{
- if (i2c_bus_busy(bus)) {
- I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
- node->bh = bh;
+ I2CPendingMaster *node = g_new(struct I2CPendingMaster, 1);
+ node->bh = bh;
+
+ QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
+}
+
+void i2c_schedule_pending_master(I2CBus *bus)
+{
+ I2CPendingMaster *node;
- QSIMPLEQ_INSERT_TAIL(&bus->pending_masters, node, entry);
+ if (i2c_bus_busy(bus)) {
+ /* someone is already controlling the bus; wait for it to release it */
+ return;
+ }
+ if (QSIMPLEQ_EMPTY(&bus->pending_masters)) {
return;
}
- bus->bh = bh;
+ node = QSIMPLEQ_FIRST(&bus->pending_masters);
+ bus->bh = node->bh;
+
+ QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
+ g_free(node);
+
qemu_bh_schedule(bus->bh);
}
void i2c_bus_release(I2CBus *bus)
{
bus->bh = NULL;
+
+ i2c_schedule_pending_master(bus);
}
int i2c_start_recv(I2CBus *bus, uint8_t address)
@@ -234,16 +251,6 @@ void i2c_end_transfer(I2CBus *bus)
g_free(node);
}
bus->broadcast = false;
-
- if (!QSIMPLEQ_EMPTY(&bus->pending_masters)) {
- I2CPendingMaster *node = QSIMPLEQ_FIRST(&bus->pending_masters);
- bus->bh = node->bh;
-
- QSIMPLEQ_REMOVE_HEAD(&bus->pending_masters, entry);
- g_free(node);
-
- qemu_bh_schedule(bus->bh);
- }
}
int i2c_send(I2CBus *bus, uint8_t data)
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 03/11] hw/misc: add a toy i2c echo device
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 01/11] readline: fix hmp completion issue Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 02/11] hw/i2c: only schedule pending master when bus is idle Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-08-22 17:20 ` Thomas Huth
2023-03-01 16:56 ` [PATCH v2 04/11] tests/avocado/machine_aspeed.py: Add an I2C slave test Cédric Le Goater
` (7 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery, Klaus Jensen,
Cédric Le Goater
From: Klaus Jensen <k.jensen@samsung.com>
Add an example I2C device to demonstrate how a slave may master the bus
and send data asynchronously to another slave.
The device will echo whatever it is sent to the device identified by the
first byte received.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
[ clg: integrated fixes :
https://lore.kernel.org/qemu-devel/Y3yMKAhOkYGtnkOp@cormorant.local/ ]
Message-Id: <20220601210831.67259-7-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/misc/i2c-echo.c | 156 ++++++++++++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 2 +
2 files changed, 158 insertions(+)
create mode 100644 hw/misc/i2c-echo.c
diff --git a/hw/misc/i2c-echo.c b/hw/misc/i2c-echo.c
new file mode 100644
index 0000000000..5705ab5d73
--- /dev/null
+++ b/hw/misc/i2c-echo.c
@@ -0,0 +1,156 @@
+#include "qemu/osdep.h"
+#include "qemu/timer.h"
+#include "qemu/main-loop.h"
+#include "block/aio.h"
+#include "hw/i2c/i2c.h"
+
+#define TYPE_I2C_ECHO "i2c-echo"
+OBJECT_DECLARE_SIMPLE_TYPE(I2CEchoState, I2C_ECHO)
+
+enum i2c_echo_state {
+ I2C_ECHO_STATE_IDLE,
+ I2C_ECHO_STATE_START_SEND,
+ I2C_ECHO_STATE_ACK,
+};
+
+typedef struct I2CEchoState {
+ I2CSlave parent_obj;
+
+ I2CBus *bus;
+
+ enum i2c_echo_state state;
+ QEMUBH *bh;
+
+ unsigned int pos;
+ uint8_t data[3];
+} I2CEchoState;
+
+static void i2c_echo_bh(void *opaque)
+{
+ I2CEchoState *state = opaque;
+
+ switch (state->state) {
+ case I2C_ECHO_STATE_IDLE:
+ return;
+
+ case I2C_ECHO_STATE_START_SEND:
+ if (i2c_start_send_async(state->bus, state->data[0])) {
+ goto release_bus;
+ }
+
+ state->pos++;
+ state->state = I2C_ECHO_STATE_ACK;
+ return;
+
+ case I2C_ECHO_STATE_ACK:
+ if (state->pos > 2) {
+ break;
+ }
+
+ if (i2c_send_async(state->bus, state->data[state->pos++])) {
+ break;
+ }
+
+ return;
+ }
+
+
+ i2c_end_transfer(state->bus);
+release_bus:
+ i2c_bus_release(state->bus);
+
+ state->state = I2C_ECHO_STATE_IDLE;
+}
+
+static int i2c_echo_event(I2CSlave *s, enum i2c_event event)
+{
+ I2CEchoState *state = I2C_ECHO(s);
+
+ switch (event) {
+ case I2C_START_RECV:
+ state->pos = 0;
+
+ break;
+
+ case I2C_START_SEND:
+ state->pos = 0;
+
+ break;
+
+ case I2C_FINISH:
+ state->pos = 0;
+ state->state = I2C_ECHO_STATE_START_SEND;
+ i2c_bus_master(state->bus, state->bh);
+
+ break;
+
+ case I2C_NACK:
+ break;
+
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+static uint8_t i2c_echo_recv(I2CSlave *s)
+{
+ I2CEchoState *state = I2C_ECHO(s);
+
+ if (state->pos > 2) {
+ return 0xff;
+ }
+
+ return state->data[state->pos++];
+}
+
+static int i2c_echo_send(I2CSlave *s, uint8_t data)
+{
+ I2CEchoState *state = I2C_ECHO(s);
+
+ if (state->pos > 2) {
+ return -1;
+ }
+
+ state->data[state->pos++] = data;
+
+ return 0;
+}
+
+static void i2c_echo_realize(DeviceState *dev, Error **errp)
+{
+ I2CEchoState *state = I2C_ECHO(dev);
+ BusState *bus = qdev_get_parent_bus(dev);
+
+ state->bus = I2C_BUS(bus);
+ state->bh = qemu_bh_new(i2c_echo_bh, state);
+
+ return;
+}
+
+static void i2c_echo_class_init(ObjectClass *oc, void *data)
+{
+ I2CSlaveClass *sc = I2C_SLAVE_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = i2c_echo_realize;
+
+ sc->event = i2c_echo_event;
+ sc->recv = i2c_echo_recv;
+ sc->send = i2c_echo_send;
+}
+
+static const TypeInfo i2c_echo = {
+ .name = TYPE_I2C_ECHO,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(I2CEchoState),
+ .class_init = i2c_echo_class_init,
+};
+
+static void register_types(void)
+{
+ type_register_static(&i2c_echo);
+}
+
+type_init(register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index fe869b98ca..a40245ad44 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -128,6 +128,8 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))
softmmu_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_ahb_apb_pnp.c'))
+softmmu_ss.add(when: 'CONFIG_I2C', if_true: files('i2c-echo.c'))
+
specific_ss.add(when: 'CONFIG_AVR_POWER', if_true: files('avr_power.c'))
specific_ss.add(when: 'CONFIG_MAC_VIA', if_true: files('mac_via.c'))
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 03/11] hw/misc: add a toy i2c echo device
2023-03-01 16:56 ` [PATCH v2 03/11] hw/misc: add a toy i2c echo device Cédric Le Goater
@ 2023-08-22 17:20 ` Thomas Huth
2023-08-23 7:14 ` Klaus Jensen
0 siblings, 1 reply; 17+ messages in thread
From: Thomas Huth @ 2023-08-22 17:20 UTC (permalink / raw)
To: qemu-arm, qemu-devel, Klaus Jensen
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
On 01/03/2023 17.56, Cédric Le Goater wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add an example I2C device to demonstrate how a slave may master the bus
> and send data asynchronously to another slave.
>
> The device will echo whatever it is sent to the device identified by the
> first byte received.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> [ clg: integrated fixes :
> https://lore.kernel.org/qemu-devel/Y3yMKAhOkYGtnkOp@cormorant.local/ ]
> Message-Id: <20220601210831.67259-7-its@irrelevant.dk>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/misc/i2c-echo.c | 156 ++++++++++++++++++++++++++++++++++++++++++++
> hw/misc/meson.build | 2 +
> 2 files changed, 158 insertions(+)
> create mode 100644 hw/misc/i2c-echo.c
>
> diff --git a/hw/misc/i2c-echo.c b/hw/misc/i2c-echo.c
> new file mode 100644
> index 0000000000..5705ab5d73
> --- /dev/null
> +++ b/hw/misc/i2c-echo.c
> @@ -0,0 +1,156 @@
> +#include "qemu/osdep.h"
> +#include "qemu/timer.h"
> +#include "qemu/main-loop.h"
> +#include "block/aio.h"
> +#include "hw/i2c/i2c.h"
Hi Klaus,
I've got two questions with regards to this new devices:
1) The file lacks a license statement (and a short comment at the beginning
what it is all about). Could you maybe provide a follow up patch with a
proper header comment that includes a license and a short description about
the device?
2) Why is it in hw/misc/ and not in hw/i2c/ ?
I think we should also have a proper Kconfig switch for this device, so we
can disable it with --without-default-devices, what do you think?
Thomas
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 03/11] hw/misc: add a toy i2c echo device
2023-08-22 17:20 ` Thomas Huth
@ 2023-08-23 7:14 ` Klaus Jensen
0 siblings, 0 replies; 17+ messages in thread
From: Klaus Jensen @ 2023-08-23 7:14 UTC (permalink / raw)
To: Thomas Huth
Cc: qemu-arm, qemu-devel, Klaus Jensen, Peter Maydell, Joel Stanley,
Andrew Jeffery, Cédric Le Goater,
Philippe Mathieu-Daudé
[-- Attachment #1: Type: text/plain, Size: 2084 bytes --]
On Aug 22 19:20, Thomas Huth wrote:
> On 01/03/2023 17.56, Cédric Le Goater wrote:
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > Add an example I2C device to demonstrate how a slave may master the bus
> > and send data asynchronously to another slave.
> >
> > The device will echo whatever it is sent to the device identified by the
> > first byte received.
> >
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> > [ clg: integrated fixes :
> > https://lore.kernel.org/qemu-devel/Y3yMKAhOkYGtnkOp@cormorant.local/ ]
> > Message-Id: <20220601210831.67259-7-its@irrelevant.dk>
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > ---
> > hw/misc/i2c-echo.c | 156 ++++++++++++++++++++++++++++++++++++++++++++
> > hw/misc/meson.build | 2 +
> > 2 files changed, 158 insertions(+)
> > create mode 100644 hw/misc/i2c-echo.c
> >
> > diff --git a/hw/misc/i2c-echo.c b/hw/misc/i2c-echo.c
> > new file mode 100644
> > index 0000000000..5705ab5d73
> > --- /dev/null
> > +++ b/hw/misc/i2c-echo.c
> > @@ -0,0 +1,156 @@
> > +#include "qemu/osdep.h"
> > +#include "qemu/timer.h"
> > +#include "qemu/main-loop.h"
> > +#include "block/aio.h"
> > +#include "hw/i2c/i2c.h"
>
> Hi Klaus,
>
> I've got two questions with regards to this new devices:
>
> 1) The file lacks a license statement (and a short comment at the beginning
> what it is all about). Could you maybe provide a follow up patch with a
> proper header comment that includes a license and a short description about
> the device?
>
> 2) Why is it in hw/misc/ and not in hw/i2c/ ?
>
> I think we should also have a proper Kconfig switch for this device, so we
> can disable it with --without-default-devices, what do you think?
>
> Thomas
>
>
Hi Thomas,
1) My apologies, I'll add the proper GPL license comment.
2) It's an example of using the asynchronous i2c send API. It's not a
"real" device, its more like the edu-device. A proper note in the file
should make this clear.
I'll send a patch to fix this up!
Thanks,
Klaus
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 04/11] tests/avocado/machine_aspeed.py: Add an I2C slave test
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (2 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 03/11] hw/misc: add a toy i2c echo device Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 17:44 ` Philippe Mathieu-Daudé
2023-03-01 16:56 ` [PATCH v2 05/11] hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU Cédric Le Goater
` (6 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Klaus Jensen
The Aspeed 2600 I2C controller supports a slave mode which can be
tested with the I2C echo device. Test extracted from :
https://lists.nongnu.org/archive/html/qemu-devel/2022-06/msg00183.html
Suggested-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/avocado/machine_aspeed.py | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index ddf05b3617..d2c57ccb7e 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -199,6 +199,8 @@ def test_arm_ast2600_evb_buildroot(self):
'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
self.vm.add_args('-device',
'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
+ self.vm.add_args('-device',
+ 'i2c-echo,bus=aspeed.i2c.bus.3,address=0x42');
self.do_test_arm_aspeed_buildroot_start(image_path, '0xf00')
exec_command_and_wait_for_pattern(self,
@@ -217,6 +219,14 @@ def test_arm_ast2600_evb_buildroot(self):
year = time.strftime("%Y")
exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
+ exec_command_and_wait_for_pattern(self,
+ 'echo slave-24c02 0x1064 > /sys/bus/i2c/devices/i2c-3/new_device',
+ 'i2c i2c-3: new_device: Instantiated device slave-24c02 at 0x64');
+ exec_command(self, 'i2cset -y 3 0x42 0x64 0x00 0xaa i');
+ time.sleep(0.1)
+ exec_command_and_wait_for_pattern(self,
+ 'hexdump /sys/bus/i2c/devices/3-1064/slave-eeprom',
+ '0000000 ffaa ffff ffff ffff ffff ffff ffff ffff');
self.do_test_arm_aspeed_buildroot_poweroff()
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 05/11] hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (3 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 04/11] tests/avocado/machine_aspeed.py: Add an I2C slave test Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 06/11] hw/arm/aspeed: Adding new machine Tiogapass " Cédric Le Goater
` (5 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Karthikeyan Pasupathi, Cédric Le Goater
From: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
This patch support Yosemitev2 in QEMU environment.
and introduced EEPROM BMC FRU data support "add fbyv2_bmc_fruid data"
along with the machine support.
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - commit log topic update
- Documentation update ]
Message-Id: <20230216133326.216017-1-pkarthikeyan1509@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/arm/aspeed.rst | 1 +
hw/arm/aspeed_eeprom.h | 3 +++
hw/arm/aspeed.c | 31 +++++++++++++++++++++++++++++++
hw/arm/aspeed_eeprom.c | 23 +++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 6c5b05128e..1d69b68591 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -24,6 +24,7 @@ AST2500 SoC based machines :
- ``sonorapass-bmc`` OCP SonoraPass BMC
- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
- ``g220a-bmc`` Bytedance G220A BMC
+- ``yosemitev2-bmc`` Facebook YosemiteV2 BMC
AST2600 SoC based machines :
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
index a0f848fa6e..edf18e9685 100644
--- a/hw/arm/aspeed_eeprom.h
+++ b/hw/arm/aspeed_eeprom.h
@@ -16,4 +16,7 @@ extern const size_t fby35_nic_fruid_len;
extern const size_t fby35_bb_fruid_len;
extern const size_t fby35_bmc_fruid_len;
+extern const uint8_t yosemitev2_bmc_fruid[];
+extern const size_t yosemitev2_bmc_fruid_len;
+
#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 27dda58338..3f992fea46 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -521,6 +521,15 @@ static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
TYPE_TMP105, 0x4d);
}
+static void yosemitev2_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = &bmc->soc;
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x51, 128 * KiB);
+ at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 128 * KiB,
+ yosemitev2_bmc_fruid, yosemitev2_bmc_fruid_len);
+}
+
static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
@@ -1174,6 +1183,24 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
aspeed_soc_num_cpus(amc->soc_name);
};
+static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook YosemiteV2 BMC (ARM1176)";
+ amc->soc_name = "ast2500-a1";
+ amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
+ amc->hw_strap2 = 0;
+ amc->fmc_model = "n25q256a";
+ amc->spi_model = "mx25l25635e";
+ amc->num_cs = 2;
+ amc->i2c_init = yosemitev2_bmc_i2c_init;
+ mc->default_ram_size = 512 * MiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
+};
+
static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1562,6 +1589,10 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_yosemitev2_class_init,
}, {
.name = MACHINE_TYPE_NAME("tacoma-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
index 04463acc9d..7006794654 100644
--- a/hw/arm/aspeed_eeprom.c
+++ b/hw/arm/aspeed_eeprom.c
@@ -77,6 +77,29 @@ const uint8_t fby35_bmc_fruid[] = {
0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
};
+/* Yosemite V2 BMC FRU */
+const uint8_t yosemitev2_bmc_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
+ 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
+ 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
+ 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
+ 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x32, 0x2e, 0x30, 0x20, 0x45, 0x56, 0x54,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
+ 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
+};
+
const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
+
+const size_t yosemitev2_bmc_fruid_len = sizeof(yosemitev2_bmc_fruid);
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 06/11] hw/arm/aspeed: Adding new machine Tiogapass in QEMU
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (4 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 05/11] hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 07/11] hw/at24c : modify at24c to support 1 byte address mode Cédric Le Goater
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Karthikeyan Pasupathi, Cédric Le Goater
From: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
This patch support Tiogapass in QEMU environment.
and introduced EEPROM BMC FRU data support "add tiogapass_bmc_fruid data"
along with the machine support.
Signed-off-by: Karthikeyan Pasupathi <pkarthikeyan1509@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: - commit log topic update
- checkpatch issues
- Documentation update ]
Message-Id: <20230216184342.253868-1-pkarthikeyan1509@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
docs/system/arm/aspeed.rst | 1 +
hw/arm/aspeed_eeprom.h | 3 +++
hw/arm/aspeed.c | 32 ++++++++++++++++++++++++++++++++
hw/arm/aspeed_eeprom.c | 22 ++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 1d69b68591..d4e293e7f9 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -25,6 +25,7 @@ AST2500 SoC based machines :
- ``fp5280g2-bmc`` Inspur FP5280G2 BMC
- ``g220a-bmc`` Bytedance G220A BMC
- ``yosemitev2-bmc`` Facebook YosemiteV2 BMC
+- ``tiogapass-bmc`` Facebook Tiogapass BMC
AST2600 SoC based machines :
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
index edf18e9685..86db6f0479 100644
--- a/hw/arm/aspeed_eeprom.h
+++ b/hw/arm/aspeed_eeprom.h
@@ -9,6 +9,9 @@
#include "qemu/osdep.h"
+extern const uint8_t tiogapass_bmc_fruid[];
+extern const size_t tiogapass_bmc_fruid_len;
+
extern const uint8_t fby35_nic_fruid[];
extern const uint8_t fby35_bb_fruid[];
extern const uint8_t fby35_bmc_fruid[];
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3f992fea46..6bafeb8fdd 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -539,6 +539,15 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
}
+static void tiogapass_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = &bmc->soc;
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, 128 * KiB);
+ at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 6), 0x54, 128 * KiB,
+ tiogapass_bmc_fruid, tiogapass_bmc_fruid_len);
+}
+
static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
{
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
@@ -1218,6 +1227,25 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
aspeed_soc_num_cpus(amc->soc_name);
};
+static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook Tiogapass BMC (ARM1176)";
+ amc->soc_name = "ast2500-a1";
+ amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
+ amc->hw_strap2 = 0;
+ amc->fmc_model = "n25q256a";
+ amc->spi_model = "mx25l25635e";
+ amc->num_cs = 2;
+ amc->i2c_init = tiogapass_bmc_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ mc->default_cpus = mc->min_cpus = mc->max_cpus =
+ aspeed_soc_num_cpus(amc->soc_name);
+ aspeed_soc_num_cpus(amc->soc_name);
+};
+
static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1597,6 +1625,10 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("tacoma-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_tacoma_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("tiogapass-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_tiogapass_class_init,
}, {
.name = MACHINE_TYPE_NAME("g220a-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
index 7006794654..2fb2d5dbb7 100644
--- a/hw/arm/aspeed_eeprom.c
+++ b/hw/arm/aspeed_eeprom.c
@@ -6,6 +6,27 @@
#include "aspeed_eeprom.h"
+/* Tiogapass BMC FRU */
+const uint8_t tiogapass_bmc_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
+ 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
+ 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
+ 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
+ 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x54, 0x69, 0x6f, 0x67, 0x61,
+ 0x20, 0x50, 0x61, 0x73, 0x73, 0x20, 0x53, 0x69, 0x6e, 0x67, 0x6c, 0x65,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x58, 0x58, 0x58, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
+ 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
+};
+
const uint8_t fby35_nic_fruid[] = {
0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
@@ -98,6 +119,7 @@ const uint8_t yosemitev2_bmc_fruid[] = {
0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
};
+const size_t tiogapass_bmc_fruid_len = sizeof(tiogapass_bmc_fruid);
const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 07/11] hw/at24c : modify at24c to support 1 byte address mode
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (5 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 06/11] hw/arm/aspeed: Adding new machine Tiogapass " Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 08/11] aspeed/fuji : correct the eeprom size Cédric Le Goater
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery, Sittisak Sinprem,
Peter Delevoryas, Cédric Le Goater
From: Sittisak Sinprem <ssinprem@celestica.com>
Signed-off-by: Sittisak Sinprem <ssinprem@celestica.com>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
[ clg: checkpatch issues ]
Message-Id: <167660539263.10409.9736070122710923479-1@git.sr.ht>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/nvram/eeprom_at24c.c | 30 +++++++++++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c
index 3328c32814..613c4929e3 100644
--- a/hw/nvram/eeprom_at24c.c
+++ b/hw/nvram/eeprom_at24c.c
@@ -41,6 +41,13 @@ struct EEPROMState {
uint16_t cur;
/* total size in bytes */
uint32_t rsize;
+ /*
+ * address byte number
+ * for 24c01, 24c02 size <= 256 byte, use only 1 byte
+ * otherwise size > 256, use 2 byte
+ */
+ uint8_t asize;
+
bool writable;
/* cells changed since last START? */
bool changed;
@@ -91,7 +98,11 @@ uint8_t at24c_eeprom_recv(I2CSlave *s)
EEPROMState *ee = AT24C_EE(s);
uint8_t ret;
- if (ee->haveaddr == 1) {
+ /*
+ * If got the byte address but not completely with address size
+ * will return the invalid value
+ */
+ if (ee->haveaddr > 0 && ee->haveaddr < ee->asize) {
return 0xff;
}
@@ -108,11 +119,11 @@ int at24c_eeprom_send(I2CSlave *s, uint8_t data)
{
EEPROMState *ee = AT24C_EE(s);
- if (ee->haveaddr < 2) {
+ if (ee->haveaddr < ee->asize) {
ee->cur <<= 8;
ee->cur |= data;
ee->haveaddr++;
- if (ee->haveaddr == 2) {
+ if (ee->haveaddr == ee->asize) {
ee->cur %= ee->rsize;
DPRINTK("Set pointer %04x\n", ee->cur);
}
@@ -199,6 +210,18 @@ static void at24c_eeprom_realize(DeviceState *dev, Error **errp)
}
DPRINTK("Reset read backing file\n");
}
+
+ /*
+ * If address size didn't define with property set
+ * value is 0 as default, setting it by Rom size detecting.
+ */
+ if (ee->asize == 0) {
+ if (ee->rsize <= 256) {
+ ee->asize = 1;
+ } else {
+ ee->asize = 2;
+ }
+ }
}
static
@@ -213,6 +236,7 @@ void at24c_eeprom_reset(DeviceState *state)
static Property at24c_eeprom_props[] = {
DEFINE_PROP_UINT32("rom-size", EEPROMState, rsize, 0),
+ DEFINE_PROP_UINT8("address-size", EEPROMState, asize, 0),
DEFINE_PROP_BOOL("writable", EEPROMState, writable, true),
DEFINE_PROP_DRIVE("drive", EEPROMState, blk),
DEFINE_PROP_END_OF_LIST()
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 08/11] aspeed/fuji : correct the eeprom size
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (6 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 07/11] hw/at24c : modify at24c to support 1 byte address mode Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC Cédric Le Goater
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery, Sittisak Sinprem,
Peter Delevoryas, Cédric Le Goater
From: Sittisak Sinprem <ssinprem@celestica.com>
Device 24C64 the size is 64 kilobits = 8kilobyte
Device 24C02 the size is 2 kilobits = 256byte
Signed-off-by: Sittisak Sinprem <ssinprem@celestica.com>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
[ clg: checkpatch issues ]
Message-Id: <167660539263.10409.9736070122710923479-2@git.sr.ht>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 36 ++++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6bafeb8fdd..cb59a37b07 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -858,42 +858,46 @@ static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
- at24c_eeprom_init(i2c[19], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[20], 0x50, 2 * KiB);
- at24c_eeprom_init(i2c[22], 0x52, 2 * KiB);
+ /*
+ * EEPROM 24c64 size is 64Kbits or 8 Kbytes
+ * 24c02 size is 2Kbits or 256 bytes
+ */
+ at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[20], 0x50, 256);
+ at24c_eeprom_init(i2c[22], 0x52, 256);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
- at24c_eeprom_init(i2c[8], 0x51, 64 * KiB);
+ at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
- at24c_eeprom_init(i2c[50], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
- at24c_eeprom_init(i2c[65], 0x53, 64 * KiB);
+ at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
- at24c_eeprom_init(i2c[68], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[69], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[70], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[71], 0x52, 64 * KiB);
+ at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[73], 0x53, 64 * KiB);
+ at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
- at24c_eeprom_init(i2c[76], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[77], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[78], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[79], 0x52, 64 * KiB);
- at24c_eeprom_init(i2c[28], 0x50, 2 * KiB);
+ at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[28], 0x50, 256);
for (int i = 0; i < 8; i++) {
at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (7 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 08/11] aspeed/fuji : correct the eeprom size Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 17:52 ` Philippe Mathieu-Daudé
2023-03-01 16:56 ` [PATCH v2 10/11] aspeed: Add a boot_rom overlap region in the SoC spi_boot container Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 11/11] aspeed/smc: Replace SysBus IRQs with GPIO lines Cédric Le Goater
10 siblings, 1 reply; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
The default boot address of the Aspeed SoCs is 0x0. For this reason,
the FMC flash device contents are remapped by HW on the first 256MB of
the address space. In QEMU, this is currently done in the machine init
with the setup of a region alias.
Move this code to the SoC and introduce an extra container to prepare
ground for the boot ROM region which will overlap the FMC flash
remapping.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 5 +++++
hw/arm/aspeed.c | 13 +------------
hw/arm/aspeed_ast2600.c | 13 +++++++++++++
hw/arm/aspeed_soc.c | 14 ++++++++++++++
hw/arm/fby35.c | 8 +-------
5 files changed, 34 insertions(+), 19 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index bd1e03e78a..8adff70072 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -58,6 +58,8 @@ struct AspeedSoCState {
MemoryRegion *dram_mr;
MemoryRegion dram_container;
MemoryRegion sram;
+ MemoryRegion spi_boot_container;
+ MemoryRegion spi_boot;
AspeedVICState vic;
AspeedRtcState rtc;
AspeedTimerCtrlState timerctrl;
@@ -120,6 +122,7 @@ struct AspeedSoCClass {
enum {
+ ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
@@ -190,6 +193,8 @@ enum {
ASPEED_DEV_JTAG1,
};
+#define ASPEED_SOC_SPI_BOOT_ADDR 0x0
+
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cb59a37b07..4a2814b7ea 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -388,18 +388,7 @@ static void aspeed_machine_init(MachineState *machine)
MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
uint64_t size = memory_region_size(&fl->mmio);
- /*
- * create a ROM region using the default mapping window size of
- * the flash module. The window size is 64MB for the AST2400
- * SoC and 128MB for the AST2500 SoC, which is twice as big as
- * needed by the flash modules of the Aspeed machines.
- */
- if (ASPEED_MACHINE(machine)->mmio_exec) {
- memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
- &fl->mmio, 0, size);
- memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
- boot_rom);
- } else {
+ if (!ASPEED_MACHINE(machine)->mmio_exec) {
memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
size, &error_abort);
memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bb2769df04..1bf1246148 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -21,6 +21,7 @@
#define ASPEED_SOC_DPMCU_SIZE 0x00040000
static const hwaddr aspeed_soc_ast2600_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_SRAM] = 0x10000000,
[ASPEED_DEV_DPMCU] = 0x18000000,
/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
@@ -282,6 +283,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
qemu_irq irq;
g_autofree char *sram_name = NULL;
+ /* Default boot region (SPI memory or ROMs) */
+ memory_region_init(&s->spi_boot_container, OBJECT(s),
+ "aspeed.spi_boot_container", 0x10000000);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
+ &s->spi_boot_container);
+
/* IO space */
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
@@ -431,6 +438,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ /* Set up an alias on the FMC CE0 region (boot default) */
+ MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
+ memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
+ fmc0_mmio, 0, memory_region_size(fmc0_mmio));
+ memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
+
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
object_property_set_link(OBJECT(&s->spi[i]), "dram",
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index e884d6badc..bf22258de9 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -25,6 +25,7 @@
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
static const hwaddr aspeed_soc_ast2400_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
@@ -59,6 +60,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
};
static const hwaddr aspeed_soc_ast2500_memmap[] = {
+ [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR,
[ASPEED_DEV_IOMEM] = 0x1E600000,
[ASPEED_DEV_FMC] = 0x1E620000,
[ASPEED_DEV_SPI1] = 0x1E630000,
@@ -245,6 +247,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
g_autofree char *sram_name = NULL;
+ /* Default boot region (SPI memory or ROMs) */
+ memory_region_init(&s->spi_boot_container, OBJECT(s),
+ "aspeed.spi_boot_container", 0x10000000);
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT],
+ &s->spi_boot_container);
+
/* IO space */
aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
sc->memmap[ASPEED_DEV_IOMEM],
@@ -354,6 +362,12 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
+ /* Set up an alias on the FMC CE0 region (boot default) */
+ MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio;
+ memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot",
+ fmc0_mmio, 0, memory_region_size(fmc0_mmio));
+ memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot);
+
/* SPI */
for (i = 0; i < sc->spis_num; i++) {
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index 90c04bbc33..f4600c290b 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -100,13 +100,7 @@ static void fby35_bmc_init(Fby35State *s)
MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
uint64_t size = memory_region_size(&fl->mmio);
- if (s->mmio_exec) {
- memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
- &fl->mmio, 0, size);
- memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE_ADDR,
- boot_rom);
- } else {
-
+ if (!s->mmio_exec) {
memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
size, &error_abort);
memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE_ADDR,
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC
2023-03-01 16:56 ` [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC Cédric Le Goater
@ 2023-03-01 17:52 ` Philippe Mathieu-Daudé
2023-03-02 9:02 ` Cédric Le Goater
0 siblings, 1 reply; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-01 17:52 UTC (permalink / raw)
To: Cédric Le Goater, qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery
On 1/3/23 17:56, Cédric Le Goater wrote:
> The default boot address of the Aspeed SoCs is 0x0. For this reason,
> the FMC flash device contents are remapped by HW on the first 256MB of
> the address space. In QEMU, this is currently done in the machine init
> with the setup of a region alias.
>
> Move this code to the SoC and introduce an extra container to prepare
> ground for the boot ROM region which will overlap the FMC flash
> remapping.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/arm/aspeed_soc.h | 5 +++++
> hw/arm/aspeed.c | 13 +------------
> hw/arm/aspeed_ast2600.c | 13 +++++++++++++
> hw/arm/aspeed_soc.c | 14 ++++++++++++++
Why aspeed2600 duplicates a lot of aspeed_soc_init() /
aspeed_soc_realize() while inheriting from TYPE_ASPEED_SOC?
Is that on purpose or because not using device_class_set_parent_realize?
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> hw/arm/fby35.c | 8 +-------
> 5 files changed, 34 insertions(+), 19 deletions(-)
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC
2023-03-01 17:52 ` Philippe Mathieu-Daudé
@ 2023-03-02 9:02 ` Cédric Le Goater
0 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-02 9:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery
On 3/1/23 18:52, Philippe Mathieu-Daudé wrote:
> On 1/3/23 17:56, Cédric Le Goater wrote:
>> The default boot address of the Aspeed SoCs is 0x0. For this reason,
>> the FMC flash device contents are remapped by HW on the first 256MB of
>> the address space. In QEMU, this is currently done in the machine init
>> with the setup of a region alias.
>>
>> Move this code to the SoC and introduce an extra container to prepare
>> ground for the boot ROM region which will overlap the FMC flash
>> remapping.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> include/hw/arm/aspeed_soc.h | 5 +++++
>> hw/arm/aspeed.c | 13 +------------
>> hw/arm/aspeed_ast2600.c | 13 +++++++++++++
>> hw/arm/aspeed_soc.c | 14 ++++++++++++++
>
> Why aspeed2600 duplicates a lot of aspeed_soc_init() /
> aspeed_soc_realize() while inheriting from TYPE_ASPEED_SOC?
We thought, back in 2019 or so, that duplicating the models was a better
approach to keep a clear understanding of the SoCs and their differences.
I agree they are very similar and maybe that was not the best solution.
OTOH, AST2600 has being receiving the most attention since it is the
latest.
The common TYPE_ASPEED_SOC is required to share a few properties at the
board level if I remember well.
Thanks,
C.
> Is that on purpose or because not using device_class_set_parent_realize?
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>
>> hw/arm/fby35.c | 8 +-------
>> 5 files changed, 34 insertions(+), 19 deletions(-)
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v2 10/11] aspeed: Add a boot_rom overlap region in the SoC spi_boot container
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (8 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 09/11] aspeed: Introduce a spi_boot region under the SoC Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
2023-03-01 16:56 ` [PATCH v2 11/11] aspeed/smc: Replace SysBus IRQs with GPIO lines Cédric Le Goater
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater
To avoid the SPI transactions fetching instructions from the FMC CE0
flash device and speed up boot, a ROM can be created if a drive is
available.
Reverse the logic to allow a machine to boot without a drive, using a
block device instead :
-blockdev node-name=fmc0,driver=file,filename=/path/to/flash.img \
-device mx66u51235f,bus=ssi.0,drive=fmc0
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 47 +++++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 4a2814b7ea..e2617388ad 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -241,12 +241,9 @@ static void aspeed_reset_secondary(ARMCPU *cpu,
cpu_set_pc(cs, info->smp_loader_start);
}
-#define FIRMWARE_ADDR 0x0
-
-static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
+static void write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
Error **errp)
{
- BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
g_autofree void *storage = NULL;
int64_t size;
@@ -272,6 +269,22 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
}
+/*
+ * Create a ROM and copy the flash contents at the expected address
+ * (0x0). Boots faster than execute-in-place.
+ */
+static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
+ uint64_t rom_size)
+{
+ MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
+
+ memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size,
+ &error_abort);
+ memory_region_add_subregion_overlap(&soc->spi_boot_container, 0,
+ boot_rom, 1);
+ write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort);
+}
+
void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
unsigned int count, int unit0)
{
@@ -332,7 +345,6 @@ static void aspeed_machine_init(MachineState *machine)
AspeedMachineState *bmc = ASPEED_MACHINE(machine);
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
AspeedSoCClass *sc;
- DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
int i;
NICInfo *nd = &nd_table[0];
@@ -382,21 +394,6 @@ static void aspeed_machine_init(MachineState *machine)
bmc->spi_model ? bmc->spi_model : amc->spi_model,
1, amc->num_cs);
- /* Install first FMC flash content as a boot rom. */
- if (drive0) {
- AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
- MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
- uint64_t size = memory_region_size(&fl->mmio);
-
- if (!ASPEED_MACHINE(machine)->mmio_exec) {
- memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
- size, &error_abort);
- memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
- boot_rom);
- write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
- }
- }
-
if (machine->kernel_filename && sc->num_cpus > 1) {
/* With no u-boot we must set up a boot stub for the secondary CPU */
MemoryRegion *smpboot = g_new(MemoryRegion, 1);
@@ -427,6 +424,16 @@ static void aspeed_machine_init(MachineState *machine)
drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
}
+ if (!bmc->mmio_exec) {
+ DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0);
+
+ if (mtd0) {
+ uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot);
+ aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0),
+ rom_size);
+ }
+ }
+
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v2 11/11] aspeed/smc: Replace SysBus IRQs with GPIO lines
2023-03-01 16:56 [PATCH v2 00/11] aspeed queue Cédric Le Goater
` (9 preceding siblings ...)
2023-03-01 16:56 ` [PATCH v2 10/11] aspeed: Add a boot_rom overlap region in the SoC spi_boot container Cédric Le Goater
@ 2023-03-01 16:56 ` Cédric Le Goater
10 siblings, 0 replies; 17+ messages in thread
From: Cédric Le Goater @ 2023-03-01 16:56 UTC (permalink / raw)
To: qemu-arm, qemu-devel
Cc: Peter Maydell, Joel Stanley, Andrew Jeffery,
Cédric Le Goater, Philippe Mathieu-Daudé
It's cleaner and removes the curious '+ 1' required to skip the DMA
IRQ line of the controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/arm/aspeed.c | 2 +-
hw/ssi/aspeed_smc.c | 5 +----
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e2617388ad..86601cb1a5 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -306,7 +306,7 @@ void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
- sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
+ qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line);
}
}
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 22df4be528..7281169322 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1134,10 +1134,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
/* Setup cs_lines for peripherals */
s->cs_lines = g_new0(qemu_irq, asc->cs_num_max);
-
- for (i = 0; i < asc->cs_num_max; ++i) {
- sysbus_init_irq(sbd, &s->cs_lines[i]);
- }
+ qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max);
/* The memory region for the controller registers */
memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s,
--
2.39.2
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