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([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id c11-20020a5d528b000000b0021e42e7c7dbsm11189566wrv.83.2022.09.06.02.28.33 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Sep 2022 02:28:33 -0700 (PDT) Message-ID: Date: Tue, 6 Sep 2022 10:28:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v4 0/7] tcg: pc-relative translation blocks Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org References: <20220906091126.298041-1-richard.henderson@linaro.org> In-Reply-To: <20220906091126.298041-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -37 X-Spam_score: -3.8 X-Spam_bar: --- X-Spam_report: (-3.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.716, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/6/22 10:11, Richard Henderson wrote: > The goal here is to reduce the amount of code generation when the > guest kernel enables address space randomization. This requires > extensive changes to each target, so opt-in with TARGET_TB_PCREL. > > This is split out of v3, which also contained target/arm changes, > as I now have patches for x86 and s390x as well. > > > r~ > > > Based-on: 20220905202259.189852-1-richard.henderson@linaro.org > ("[PATCH v3 0/6] tcg: Introduce CPUTLBEntryFull") > > v2: https://lore.kernel.org/qemu-devel/20220816203400.161187-1-richard.henderson@linaro.org/ > v3: https://lore.kernel.org/qemu-devel/20220822232338.1727934-1-richard.henderson@linaro.org/ > > branch: https://gitlab.com/rth7680/qemu/-/tree/tcg-pcrel Arg. Accidentally dropped a patch from v3: > > > Richard Henderson (7): > accel/tcg: Use bool for page_find_alloc > accel/tcg: Use DisasContextBase in plugin_gen_tb_start > accel/tcg: Do not align tb->page_addr[0] > include/hw/core: Create struct CPUJumpCache > accel/tcg: Introduce tb_pc and tb_pc_log > accel/tcg: Introduce TARGET_TB_PCREL > accel/tcg: Split log_cpu_exec into inline and slow path > > include/exec/cpu-defs.h | 3 + > include/exec/exec-all.h | 51 ++++++++++- > include/exec/plugin-gen.h | 7 +- > include/hw/core/cpu.h | 9 +- > accel/tcg/cpu-exec.c | 108 ++++++++++++++++-------- > accel/tcg/cputlb.c | 5 +- > accel/tcg/plugin-gen.c | 22 ++--- > accel/tcg/translate-all.c | 90 ++++++++++++-------- > accel/tcg/translator.c | 2 +- > target/arm/cpu.c | 4 +- > target/avr/cpu.c | 2 +- > target/hexagon/cpu.c | 2 +- > target/hppa/cpu.c | 4 +- > target/i386/tcg/tcg-cpu.c | 2 +- > target/loongarch/cpu.c | 2 +- > target/microblaze/cpu.c | 2 +- > target/mips/tcg/exception.c | 2 +- > target/mips/tcg/sysemu/special_helper.c | 2 +- > target/openrisc/cpu.c | 2 +- > target/riscv/cpu.c | 4 +- > target/rx/cpu.c | 2 +- > target/sh4/cpu.c | 4 +- > target/sparc/cpu.c | 2 +- > target/tricore/cpu.c | 2 +- > tcg/tcg.c | 6 +- > 25 files changed, 226 insertions(+), 115 deletions(-) >