From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ecNSX-0005J2-Kg for qemu-devel@nongnu.org; Thu, 18 Jan 2018 22:35:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ecNSU-0005T1-BC for qemu-devel@nongnu.org; Thu, 18 Jan 2018 22:35:17 -0500 Received: from mx1.redhat.com ([209.132.183.28]:20137) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ecNST-0005So-TW for qemu-devel@nongnu.org; Thu, 18 Jan 2018 22:35:14 -0500 References: <1516308132-10272-1-git-send-email-mst@redhat.com> <1516308132-10272-13-git-send-email-mst@redhat.com> From: Jason Wang Message-ID: Date: Fri, 19 Jan 2018 11:34:57 +0800 MIME-Version: 1.0 In-Reply-To: <1516308132-10272-13-git-send-email-mst@redhat.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL v4 12/29] intel-iommu: Extend address width to 48 bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , qemu-devel@nongnu.org Cc: Peter Maydell , Eduardo Habkost , Peter Xu , Prasad Singamsetty , Paolo Bonzini , Marcel Apfelbaum , Igor Mammedov , Richard Henderson , Prasad Singamsetty On 2018=E5=B9=B401=E6=9C=8819=E6=97=A5 04:45, Michael S. Tsirkin wrote: > From: Prasad Singamsetty > > The current implementation of Intel IOMMU code only supports 39 bits > iova address width. This patch provides a new parameter (x-aw-bits) > for intel-iommu to extend its address width to 48 bits but keeping the > default the same (39 bits). The reason for not changing the default > is to avoid potential compatibility problems with live migration of > intel-iommu enabled QEMU guest. The only valid values for 'x-aw-bits' > parameter are 39 and 48. > > After enabling larger address width (48), we should be able to map > larger iova addresses in the guest. For example, a QEMU guest that > is configured with large memory ( >=3D1TB ). To check whether 48 bits > aw is enabled, we can grep in the guest dmesg output with line: > "DMAR: Host address width 48". > > Signed-off-by: Prasad Singamsetty > Reviewed-by: Peter Xu > Reviewed-by: Michael S. Tsirkin > Signed-off-by: Michael S. Tsirkin > --- > hw/i386/intel_iommu_internal.h | 9 ++-- > include/hw/i386/intel_iommu.h | 1 + > hw/i386/acpi-build.c | 3 +- > hw/i386/intel_iommu.c | 101 ++++++++++++++++++++++++--------= --------- > 4 files changed, 65 insertions(+), 49 deletions(-) > [...] > =20 > /* DMA Remapping Fault Conditions */ > typedef enum VTDFaultReason { > @@ -360,8 +358,7 @@ typedef union VTDInvDesc VTDInvDesc; > #define VTD_INV_DESC_IOTLB_DOMAIN (2ULL << 4) > #define VTD_INV_DESC_IOTLB_PAGE (3ULL << 4) > #define VTD_INV_DESC_IOTLB_DID(val) (((val) >> 16) & VTD_DOMAIN_I= D_MASK) > -#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL & \ > - ((1ULL << VTD_MGAW) - 1)) > +#define VTD_INV_DESC_IOTLB_ADDR(val) ((val) & ~0xfffULL) > #define VTD_INV_DESC_IOTLB_AM(val) ((val) & 0x3fULL) > #define VTD_INV_DESC_IOTLB_RSVD_LO 0xffffffff0000ff00ULL > #define VTD_INV_DESC_IOTLB_RSVD_HI 0xf80ULL > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iomm= u.h > index 372b06d..45ec891 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -304,6 +304,7 @@ struct IntelIOMMUState { > bool intr_eime; /* Extended interrupt mode enable= d */ > OnOffAuto intr_eim; /* Toggle for EIM cabability */ > bool buggy_eim; /* Force buggy EIM unless eim=3Do= ff */ > + uint8_t aw_bits; /* Host/IOVA address width (in bit= s) */ > }; Consider it's guest visible, do we need to migrate this ? Thanks