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Fri, 20 Sep 2024 09:24:23 +0000 (GMT) Message-ID: Subject: Re: [PATCH] target/ppc: Fix lxvx/stxvx facility check From: Ilya Leoshkevich To: Claudio Fontana , Fabiano Rosas , qemu-devel@nongnu.org, Richard Henderson Cc: qemu-stable@nongnu.org, Nicholas Piggin , Daniel Henrique Barboza Date: Fri, 20 Sep 2024 11:24:23 +0200 In-Reply-To: References: <20240911141651.6914-1-farosas@suse.de> <9e6212ca-5c2f-459c-a59d-11fbdb796c07@suse.de> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: FuYetwBzBNMTFG9MEe9kmBYksJ41KO-s X-Proofpoint-ORIG-GUID: jkDDeCZ0hSSW_DObsB2I0Lp1o8biFUdU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-20_04,2024-09-19_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 mlxscore=0 clxscore=1011 malwarescore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409200063 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 2024-09-19 at 13:36 +0200, Claudio Fontana wrote: > ping, adding Richard. >=20 > We will need to include this downstream because of the breakage its > lack causes. > It is already reviewed by me, but some TCG maintainer indicating it > will be included in some queue would help, >=20 > Thanks, >=20 > Claudio >=20 > On 9/18/24 17:11, Claudio Fontana wrote: > > Adding Ilya FYI. > >=20 > > Ciao, > >=20 > > Claudio > >=20 > > On 9/11/24 18:19, Claudio Fontana wrote: > > > On 9/11/24 16:16, Fabiano Rosas wrote: > > > > The XT check for the lxvx/stxvx instructions is currently > > > > inverted. This was introduced during the move to decodetree. > > > >=20 > > > > From the ISA: > > > > =C2=A0 Chapter 7. Vector-Scalar Extension Facility > > > > =C2=A0 Load VSX Vector Indexed X-form > > > >=20 > > > > =C2=A0 lxvx XT,RA,RB > > > > =C2=A0 if TX=3D0 & MSR.VSX=3D0 then VSX_Unavailable() > > > > =C2=A0 if TX=3D1 & MSR.VEC=3D0 then Vector_Unavailable() > > > > =C2=A0 ... > > > > =C2=A0 Let XT be the value 32=C3=97TX + T. > > > >=20 > > > > The code currently does the opposite: > > > >=20 > > > > =C2=A0=C2=A0=C2=A0 if (paired || a->rt >=3D 32) { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQUIRE_VSX(ctx); > > > > =C2=A0=C2=A0=C2=A0 } else { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQUIRE_VECTOR(ctx); > > > > =C2=A0=C2=A0=C2=A0 } > > > >=20 > > > > This was already fixed for lxv/stxv at commit "2cc0e449d1 > > > > (target/ppc: > > > > Fix lxv/stxv MSR facility check)", but the indexed forms were > > > > missed. > > > >=20 > > > > Cc: qemu-stable@nongnu.org > > > > Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from > > > > legacy to decodtree") > > > > Signed-off-by: Fabiano Rosas > > > > --- > > > > =C2=A0target/ppc/translate/vsx-impl.c.inc | 2 +- > > > > =C2=A01 file changed, 1 insertion(+), 1 deletion(-) > > > >=20 > > > > diff --git a/target/ppc/translate/vsx-impl.c.inc > > > > b/target/ppc/translate/vsx-impl.c.inc > > > > index 40a87ddc4a..a869f30e86 100644 > > > > --- a/target/ppc/translate/vsx-impl.c.inc > > > > +++ b/target/ppc/translate/vsx-impl.c.inc > > > > @@ -2244,7 +2244,7 @@ static bool do_lstxv_PLS_D(DisasContext > > > > *ctx, arg_PLS_D *a, > > > > =C2=A0 > > > > =C2=A0static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool > > > > store, bool paired) > > > > =C2=A0{ > > > > -=C2=A0=C2=A0=C2=A0 if (paired || a->rt >=3D 32) { > > > > +=C2=A0=C2=A0=C2=A0 if (paired || a->rt < 32) { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQUIRE_VSX(ctx); > > > > =C2=A0=C2=A0=C2=A0=C2=A0 } else { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 REQUIRE_VECTOR(ctx= ); > > >=20 > > > Reviewed-by: Claudio Fontana FWIW Acked-by: Ilya Leoshkevich But I'm not a maintainer, I guess Richard will need to pick it up.