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Mon, 15 Apr 2024 02:35:10 -0700 (PDT) Message-ID: Date: Mon, 15 Apr 2024 11:35:08 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: =?UTF-8?Q?In=C3=A8s_Varhol?= , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , qemu-arm@nongnu.org, Laurent Vivier , Samuel Tardieu , Arnaud Minier , Peter Maydell References: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> <20240414130604.182059-3-ines.varhol@telecom-paris.fr> <11343bd1-1f0d-4654-a50d-f3b19fabf9e8@linaro.org> Content-Language: en-US In-Reply-To: <11343bd1-1f0d-4654-a50d-f3b19fabf9e8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 15/4/24 11:29, Philippe Mathieu-Daudé wrote: > Hi Inès, > > On 14/4/24 15:05, Inès Varhol wrote: >> Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC >> to the optional DM163 display from the board code (GPIOs outputs need >> to be connected to both SYSCFG inputs and DM163 inputs). >> >> STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. >> >> Signed-off-by: Arnaud Minier >> Signed-off-by: Inès Varhol >> --- >>   hw/arm/stm32l4x5_soc.c              |  6 ++++-- >>   tests/qtest/stm32l4x5_gpio-test.c   | 12 +++++++----- >>   tests/qtest/stm32l4x5_syscfg-test.c | 16 +++++++++------- >>   3 files changed, 20 insertions(+), 14 deletions(-) >> >> diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c >> index 40e294f838..c4b45e6956 100644 >> --- a/hw/arm/stm32l4x5_soc.c >> +++ b/hw/arm/stm32l4x5_soc.c >> @@ -1,8 +1,8 @@ >>   /* >>    * STM32L4x5 SoC family >>    * >> - * Copyright (c) 2023 Arnaud Minier >> - * Copyright (c) 2023 Inès Varhol >> + * Copyright (c) 2024 Arnaud Minier >> + * Copyright (c) 2024 Inès Varhol > > You can keep 2023-2024. > >>    * >>    * SPDX-License-Identifier: GPL-2.0-or-later >>    * >> @@ -221,6 +221,8 @@ static void stm32l4x5_soc_realize(DeviceState >> *dev_soc, Error **errp) >>           } >>       } >> +    qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL); >> + >>       /* EXTI device */ >>       busdev = SYS_BUS_DEVICE(&s->exti); >>       if (!sysbus_realize(busdev, errp)) { >> diff --git a/tests/qtest/stm32l4x5_gpio-test.c >> b/tests/qtest/stm32l4x5_gpio-test.c >> index 0f6bda54d3..495a6fc413 100644 >> --- a/tests/qtest/stm32l4x5_gpio-test.c >> +++ b/tests/qtest/stm32l4x5_gpio-test.c >> @@ -43,6 +43,8 @@ >>   #define OTYPER_PUSH_PULL 0 >>   #define OTYPER_OPEN_DRAIN 1 >> +#define SYSCFG "/machine/soc" > > Can we have a comment such /* SoC forwards GPIOs to SysCfg */? > > (Similar comments for stm32l4x5_syscfg-test.c). Reviewed-by: Philippe Mathieu-Daudé