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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Brian Cain <brian.cain@oss.qualcomm.com>, qemu-devel@nongnu.org
Cc: ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com,
	marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com,
	sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng,
	Brian Cain <bcain@quicinc.com>
Subject: Re: [PATCH v5 19/35] target/hexagon: Add vmstate representation
Date: Wed, 25 Mar 2026 20:21:54 +0100	[thread overview]
Message-ID: <d0f113a6-0e9a-4e23-becd-9233f1abba72@linaro.org> (raw)
In-Reply-To: <20260311034923.1044737-20-brian.cain@oss.qualcomm.com>

On 11/3/26 04:49, Brian Cain wrote:
> From: Brian Cain <bcain@quicinc.com>
> 
> Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>   target/hexagon/internal.h |  4 ++++
>   target/hexagon/cpu.c      |  3 +++
>   target/hexagon/machine.c  | 32 ++++++++++++++++++++++++++++++++
>   3 files changed, 39 insertions(+)
>   create mode 100644 target/hexagon/machine.c
> 
> diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
> index 5fc837ae229..cd06ff41d4f 100644
> --- a/target/hexagon/internal.h
> +++ b/target/hexagon/internal.h
> @@ -31,4 +31,8 @@ void hexagon_debug(CPUHexagonState *env);
>   
>   extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
>   
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_hexagon_cpu;
> +#endif
> +
>   #endif
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 6fabfaad6d2..38d605b06ba 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -387,6 +387,9 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
>       cc->gdb_stop_before_watchpoint = true;
>       cc->gdb_core_xml_file = "hexagon-core.xml";
>       cc->disas_set_info = hexagon_cpu_disas_set_info;
> +#ifndef CONFIG_USER_ONLY
> +    dc->vmsd = &vmstate_hexagon_cpu;
> +#endif
>       cc->tcg_ops = &hexagon_tcg_ops;
>   }
>   
> diff --git a/target/hexagon/machine.c b/target/hexagon/machine.c
> new file mode 100644
> index 00000000000..d6dcd07dd4a
> --- /dev/null
> +++ b/target/hexagon/machine.c
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "migration/cpu.h"

We don't need to include the target-specific "migration/cpu.h" header,
the target-agnostic "migration/vmstate.h" should be sufficient. With
that change:

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

> +#include "cpu.h"
> +
> +const VMStateDescription vmstate_hexagon_cpu = {
> +    .name = "cpu",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT32_ARRAY(env.gpr, HexagonCPU, TOTAL_PER_THREAD_REGS),
> +        VMSTATE_UINT32_ARRAY(env.pred, HexagonCPU, NUM_PREGS),
> +        VMSTATE_UINT32_ARRAY(env.t_sreg, HexagonCPU, NUM_SREGS),
> +        VMSTATE_UINT32_ARRAY(env.greg, HexagonCPU, NUM_GREGS),
> +        VMSTATE_UINT32(env.next_PC, HexagonCPU),
> +        VMSTATE_UINT32(env.tlb_lock_state, HexagonCPU),
> +        VMSTATE_UINT32(env.k0_lock_state, HexagonCPU),
> +        VMSTATE_UINT32(env.tlb_lock_count, HexagonCPU),
> +        VMSTATE_UINT32(env.k0_lock_count, HexagonCPU),
> +        VMSTATE_UINT32(env.threadId, HexagonCPU),
> +        VMSTATE_UINT32(env.cause_code, HexagonCPU),
> +        VMSTATE_UINT32(env.wait_next_pc, HexagonCPU),
> +        VMSTATE_UINT64(env.t_cycle_count, HexagonCPU),
> +
> +        VMSTATE_END_OF_LIST()
> +    },
> +};



  reply	other threads:[~2026-03-25 19:22 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-11  3:48 [PATCH v5 00/35] Hexagon system emulation, Part 1/3 Brian Cain
2026-03-11  3:48 ` [PATCH v5 01/35] docs: Add hexagon sysemu docs Brian Cain
2026-03-11  3:48 ` [PATCH v5 02/35] docs/system: Add hexagon CPU emulation Brian Cain
2026-03-11  3:48 ` [PATCH v5 03/35] target/hexagon: Fix badva reference, delete CAUSE Brian Cain
2026-03-11  3:48 ` [PATCH v5 04/35] target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof Brian Cain
2026-03-11  3:48 ` [PATCH v5 05/35] target/hexagon: Handle system/guest registers in gen_analyze_funcs.py and hex_common.py Brian Cain
2026-03-11  3:48 ` [PATCH v5 06/35] target/hexagon: Suppress unused-variable warnings for sysemu source regs Brian Cain
2026-03-12 21:03   ` Taylor Simpson
2026-03-11  3:48 ` [PATCH v5 07/35] target/hexagon: Make gen_exception_end_tb non-static Brian Cain
2026-03-11  3:48 ` [PATCH v5 08/35] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags() Brian Cain via qemu development
2026-03-11  3:48 ` [PATCH v5 09/35] target/hexagon: Add privilege check, use tag_ignore() Brian Cain
2026-03-11  3:48 ` [PATCH v5 10/35] target/hexagon: Add a placeholder fp exception Brian Cain
2026-03-11  3:48 ` [PATCH v5 11/35] target/hexagon: Add guest, system reg number defs Brian Cain
2026-03-11  3:49 ` [PATCH v5 12/35] target/hexagon: Add guest, system reg number state Brian Cain
2026-03-11  3:49 ` [PATCH v5 13/35] target/hexagon: Add TCG values for sreg, greg Brian Cain
2026-03-11  3:49 ` [PATCH v5 14/35] target/hexagon: Add guest/sys reg writes to DisasContext Brian Cain
2026-03-11  3:49 ` [PATCH v5 15/35] target/hexagon: Add imported macro, attr defs for sysemu Brian Cain
2026-03-11  3:49 ` [PATCH v5 16/35] target/hexagon: Add new macro definitions " Brian Cain
2026-03-11  3:49 ` [PATCH v5 17/35] target/hexagon: Add handlers for guest/sysreg r/w Brian Cain
2026-03-11  3:49 ` [PATCH v5 18/35] target/hexagon: Add placeholder greg/sreg r/w helpers Brian Cain
2026-03-11  3:49 ` [PATCH v5 19/35] target/hexagon: Add vmstate representation Brian Cain
2026-03-25 19:21   ` Philippe Mathieu-Daudé [this message]
2026-03-11  3:49 ` [PATCH v5 20/35] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env() Brian Cain
2026-03-11  3:49 ` [PATCH v5 21/35] target/hexagon: Define register fields for system regs Brian Cain
2026-03-11  3:49 ` [PATCH v5 22/35] target/hexagon: Implement do_raise_exception() Brian Cain
2026-03-11  3:49 ` [PATCH v5 23/35] target/hexagon: Add system reg insns Brian Cain
2026-03-11  3:49 ` [PATCH v5 24/35] target/hexagon: Add sysemu TCG overrides Brian Cain
2026-03-25 19:24   ` Philippe Mathieu-Daudé
2026-03-11  3:49 ` [PATCH v5 25/35] target/hexagon: Add implicit attributes to sysemu macros Brian Cain
2026-03-11  3:49 ` [PATCH v5 26/35] target/hexagon: Add TCG overrides for int handler insts Brian Cain
2026-03-11  3:49 ` [PATCH v5 27/35] target/hexagon: Add TCG overrides for thread ctl Brian Cain
2026-03-11  3:49 ` [PATCH v5 28/35] target/hexagon: Add TCG overrides for rte, nmi Brian Cain
2026-03-11  3:49 ` [PATCH v5 29/35] target/hexagon: Add sreg_{read,write} helpers Brian Cain
2026-03-25 19:26   ` Philippe Mathieu-Daudé
2026-03-11  3:49 ` [PATCH v5 30/35] target/hexagon: Add cpu modes, mmu indices, next_PC to state Brian Cain
2026-03-11  3:49 ` [PATCH v5 31/35] hw/hexagon: Introduce hexagon TLB device Brian Cain
2026-03-25 19:38   ` Philippe Mathieu-Daudé
2026-03-11  3:49 ` [PATCH v5 32/35] target/hexagon: Add stubs for modify_ssr/get_exe_mode Brian Cain
2026-03-11  3:49 ` [PATCH v5 33/35] target/hexagon: Add clear_wait_mode() definition Brian Cain
2026-03-11  3:49 ` [PATCH v5 34/35] target/hexagon: Define f{S,G}ET_FIELD macros Brian Cain
2026-03-11  3:49 ` [PATCH v5 35/35] target/hexagon: Add hex_interrupts support Brian Cain

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