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[174.21.75.75]) by smtp.gmail.com with ESMTPSA id hk18sm82576pjb.20.2021.12.13.13.46.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Dec 2021 13:46:10 -0800 (PST) Subject: Re: [PATCH] Target/arm: Implement Cortex-A5 To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Byron Lathi References: <20211213182449.7068-1-bslathi19@gmail.com> <87wnk8i4x7.fsf@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 13 Dec 2021 13:46:09 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <87wnk8i4x7.fsf@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::431 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-4.093, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/13/21 1:02 PM, Alex Bennée wrote: >> + cpu->midr = 0x410fc0f1; > > hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but > I can't find the actual value in the TRM. https://developer.arm.com/documentation/ddi0434/c has exactly this value at the top of table 4-9. >> + cpu->reset_fpsid = 0x41023051; > > I think for the a5 the FPU is optional so maybe we need a cpu option > here? Or maybe just assume it's enabled on QEMUs version? Yeah, there's no entry for fpsid in the above manual. >> + cpu->isar.id_mmfr0 = 0x00100103; > > the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not supported. Again, this does match table 4-9. r~