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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43bd42c588dsm179071945e9.21.2025.03.10.11.34.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Mar 2025 11:34:41 -0700 (PDT) Message-ID: Date: Mon, 10 Mar 2025 19:34:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 14/14] hw/sd/sdhci: Remove unnecessary 'endianness' property To: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , Bernhard Beschow , Guenter Roeck , BALATON Zoltan Cc: qemu-devel@nongnu.org, Steven Lee , Joel Stanley , Peter Maydell , qemu-arm@nongnu.org, Andrey Smirnov , Paolo Bonzini , Bin Meng , Eduardo Habkost , qemu-ppc@nongnu.org, =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= , Andrew Jeffery , Troy Lee , Jean-Christophe Dubois , qemu-block@nongnu.org, Jamin Lin References: <20250310000620.70120-1-philmd@linaro.org> <20250310000620.70120-15-philmd@linaro.org> <0fa157de-ee4e-4b7f-b08e-bdf65e1840ad@linaro.org> <6ecc3790-e5a1-4d02-aefa-c6d632936a6a@roeck-us.net> <20adfeac-df39-45d1-9c5b-95fe7cafbbde@kaod.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20adfeac-df39-45d1-9c5b-95fe7cafbbde@kaod.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/3/25 19:24, Cédric Le Goater wrote: > On 3/10/25 18:38, Bernhard Beschow wrote: >> >> >> Am 10. März 2025 17:31:57 UTC schrieb "Philippe Mathieu-Daudé" >> : >>> On 10/3/25 16:56, Guenter Roeck wrote: >>>> On 3/10/25 08:27, Philippe Mathieu-Daudé wrote: >>>>> On 10/3/25 15:09, BALATON Zoltan wrote: >>>>>> On Mon, 10 Mar 2025, Philippe Mathieu-Daudé wrote: >>>>>>> The previous commit removed the single use of instance >>>>>>> setting the "endianness" property. >>>>>>> >>>>>>> Since classes can register their io_ops with correct >>>>>>> endianness, no need to support different ones. >>>>>>> >>>>>>> Remove the code related to SDHCIState::endianess field. >>>>>>> >>>>>>> Remove the now unused SDHCIState::io_ops field, since we >>>>>>> directly use the class one. >>>>>>> >>>>>>> Suggested-by: Bernhard Beschow >>>>>>> Signed-off-by: Philippe Mathieu-Daudé >>>>>>> --- >>>>>>> hw/sd/sdhci-internal.h |  1 - >>>>>>> include/hw/sd/sdhci.h  |  2 -- >>>>>>> hw/sd/sdhci.c          | 33 +++------------------------------ >>>>>>> 3 files changed, 3 insertions(+), 33 deletions(-) >>>>>>> >>>>>>> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h >>>>>>> index d99a8493db2..e4da6c831d1 100644 >>>>>>> --- a/hw/sd/sdhci-internal.h >>>>>>> +++ b/hw/sd/sdhci-internal.h >>>>>>> @@ -308,7 +308,6 @@ extern const VMStateDescription sdhci_vmstate; >>>>>>> #define SDHC_CAPAB_REG_DEFAULT 0x057834b4 >>>>>>> >>>>>>> #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ >>>>>>> -    DEFINE_PROP_UINT8("endianness", _state, endianness, >>>>>>> DEVICE_LITTLE_ENDIAN), \ >>>>>>>      DEFINE_PROP_UINT8("sd-spec-version", _state, >>>>>>> sd_spec_version, 2), \ >>>>>>>      DEFINE_PROP_UINT8("uhs", _state, uhs_mode, >>>>>>> UHS_NOT_SUPPORTED), \ >>>>>>>      \ >>>>>>> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h >>>>>>> index e8fced5eedc..1016a5b5b77 100644 >>>>>>> --- a/include/hw/sd/sdhci.h >>>>>>> +++ b/include/hw/sd/sdhci.h >>>>>>> @@ -54,7 +54,6 @@ struct SDHCIState { >>>>>>>      AddressSpace sysbus_dma_as; >>>>>>>      AddressSpace *dma_as; >>>>>>>      MemoryRegion *dma_mr; >>>>>>> -    const MemoryRegionOps *io_ops; >>>>>>> >>>>>>>      QEMUTimer *insert_timer;       /* timer for 'changing' sd >>>>>>> card. */ >>>>>>>      QEMUTimer *transfer_timer; >>>>>>> @@ -105,7 +104,6 @@ struct SDHCIState { >>>>>>> >>>>>>>      /* Configurable properties */ >>>>>>>      uint32_t quirks; >>>>>>> -    uint8_t endianness; >>>>>>>      uint8_t sd_spec_version; >>>>>>>      uint8_t uhs_mode; >>>>>>> }; >>>>>>> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c >>>>>>> index 47e4bd1a610..cbb9f4ae8c0 100644 >>>>>>> --- a/hw/sd/sdhci.c >>>>>>> +++ b/hw/sd/sdhci.c >>>>>>> @@ -1391,17 +1391,6 @@ sdhci_write(void *opaque, hwaddr offset, >>>>>>> uint64_t val, unsigned size) >>>>>>> } >>>>>>> >>>>>>> static const MemoryRegionOps sdhci_mmio_le_ops = { >>>>>>> -    .read = sdhci_read, >>>>>>> -    .write = sdhci_write, >>>>>>> -    .valid = { >>>>>>> -        .min_access_size = 1, >>>>>>> -        .max_access_size = 4, >>>>>>> -        .unaligned = false >>>>>>> -    }, >>>>>>> -    .endianness = DEVICE_LITTLE_ENDIAN, >>>>>>> -}; >>>>>>> - >>>>>>> -static const MemoryRegionOps sdhci_mmio_be_ops = { >>>>>>>      .read = sdhci_read, >>>>>>>      .write = sdhci_write, >>>>>>>      .impl = { >>>>>>> @@ -1413,7 +1402,7 @@ static const MemoryRegionOps >>>>>>> sdhci_mmio_be_ops = { >>>>>>>          .max_access_size = 4, >>>>>>>          .unaligned = false >>>>>>>      }, >>>>>>> -    .endianness = DEVICE_BIG_ENDIAN, >>>>>>> +    .endianness = DEVICE_LITTLE_ENDIAN, >>>>>>> }; >>>>>>> >>>>>>> static void sdhci_init_readonly_registers(SDHCIState *s, Error >>>>>>> **errp) >>>>>>> @@ -1467,23 +1456,6 @@ void sdhci_common_realize(SDHCIState *s, >>>>>>> Error **errp) >>>>>>>      SDHCIClass *sc = s->sc; >>>>>>>      const char *class_name = object_get_typename(OBJECT(s)); >>>>>>> >>>>>>> -    s->io_ops = sc->io_ops ?: &sdhci_mmio_le_ops; >>>>>>> -    switch (s->endianness) { >>>>>>> -    case DEVICE_LITTLE_ENDIAN: >>>>>>> -        /* s->io_ops is little endian by default */ >>>>>>> -        break; >>>>>>> -    case DEVICE_BIG_ENDIAN: >>>>>>> -        if (s->io_ops != &sdhci_mmio_le_ops) { >>>>>>> -            error_setg(errp, "SD controller doesn't support big >>>>>>> endianness"); >>>>>>> -            return; >>>>>>> -        } >>>>>>> -        s->io_ops = &sdhci_mmio_be_ops; >>>>>>> -        break; >>>>>>> -    default: >>>>>>> -        error_setg(errp, "Incorrect endianness"); >>>>>>> -        return; >>>>>>> -    } >>>>>>> - >>>>>>>      sdhci_init_readonly_registers(s, errp); >>>>>>>      if (*errp) { >>>>>>>          return; >>>>>>> @@ -1493,7 +1465,7 @@ void sdhci_common_realize(SDHCIState *s, >>>>>>> Error **errp) >>>>>>>      s->fifo_buffer = g_malloc0(s->buf_maxsz); >>>>>>> >>>>>>>      assert(sc->iomem_size >= SDHC_REGISTERS_MAP_SIZE); >>>>>>> -    memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, >>>>>>> class_name, >>>>>>> +    memory_region_init_io(&s->iomem, OBJECT(s), sc->io_ops, s, >>>>>>> class_name, >>>>>>>                            sc->iomem_size); >>>>>>> } >>>>>>> >>>>>>> @@ -1578,6 +1550,7 @@ void sdhci_common_class_init(ObjectClass >>>>>>> *klass, const void *data) >>>>>>>      dc->vmsd = &sdhci_vmstate; >>>>>>>      device_class_set_legacy_reset(dc, sdhci_poweron_reset); >>>>>>> >>>>>>> +    sc->io_ops = &sdhci_mmio_le_ops; >>>>>> >>>>>> You call common_class_init in subclass class_inits last so this >>>>>> would overwrite what subclass has set, doesn't it? I think you >>>>>> either have to change order in subclass class_init methods or not >>>>>> set this here. >>>>> >>>>> Oops... I'm surprised tests passed. Do we have coverage for sdhci on >>>>> e500 machines? Or are we only testing them via virtio PCI block >>>>> storage? >>>> >>>> Not sure if that is what you are asking, but I have been testing it >>>> with >>>> sdhci-pci for a long time (not this series, though). >>> >>> I'm referring to the Freescale eSDHC controller of PPC e500 machines >>> (see previous patch). >> >> I think testing SDHCI is generally difficult since the images need to >> be resized to a power of two. historical references for this "sdcard power of 2" limitation: https://lore.kernel.org/qemu-devel/20210623180021.898286-1-f4bug@amsat.org/ https://lore.kernel.org/qemu-devel/4b846383-83bf-4252-a172-95604f2f585b@linaro.org/ > Any idea how to do this with the new >> functional tests? > > we can truncate to 64M the rootfs used in  : > >    tests/functional/test_ppc64_e500.py > > and boot from it in a new test if that's supported by the machine. Yes, that is the best we can do until we implement the async DMA. Regards, Phil.