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References: <cover.1542321076.git.alistair.francis@wdc.com>
	<7961f2bc55e109ff10543c4665c5cbc3c75a5bf7.1542321076.git.alistair.francis@wdc.com>
From: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <d11e2ddb-978e-1359-16ff-4b640cd74e6d@linaro.org>
Date: Fri, 16 Nov 2018 09:59:04 +0100
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Subject: Re: [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load
 and store instructions
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:36 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
>  tcg/riscv/tcg-target.inc.c | 56 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
> 
> diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
> index 646a4d3ebd..bc433170c4 100644
> --- a/tcg/riscv/tcg-target.inc.c
> +++ b/tcg/riscv/tcg-target.inc.c
> @@ -518,6 +518,62 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
>      tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
>  }
>  
> +static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
> +                         TCGReg addr, intptr_t offset)
> +{
> +    int32_t imm12 = sextract32(offset, 0, 12);

sextract64 for rv64.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~