From: "Cédric Le Goater" <clg@kaod.org>
To: Jamin Lin <jamin_lin@aspeedtech.com>,
Peter Maydell <peter.maydell@linaro.org>,
Steven Lee <steven_lee@aspeedtech.com>,
Troy Lee <leetroy@gmail.com>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
Joel Stanley <joel@jms.id.au>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>
Cc: troy_lee@aspeedtech.com
Subject: Re: [PATCH v4 23/23] docs/specs: Add aspeed-intc
Date: Tue, 4 Mar 2025 08:26:11 +0100 [thread overview]
Message-ID: <d15c851e-355c-4abf-a97b-63df517b31be@kaod.org> (raw)
In-Reply-To: <20250303095457.2337631-24-jamin_lin@aspeedtech.com>
On 3/3/25 10:54, Jamin Lin wrote:
> Add AST2700 INTC design guidance and its block diagram.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> docs/specs/aspeed-intc.rst | 136 +++++++++++++++++++++++++++++++++++++
> docs/specs/index.rst | 1 +
> 2 files changed, 137 insertions(+)
> create mode 100644 docs/specs/aspeed-intc.rst
>
> diff --git a/docs/specs/aspeed-intc.rst b/docs/specs/aspeed-intc.rst
> new file mode 100644
> index 0000000000..9cefd7f37f
> --- /dev/null
> +++ b/docs/specs/aspeed-intc.rst
> @@ -0,0 +1,136 @@
> +===========================
> +ASPEED Interrupt Controller
> +===========================
> +
> +AST2700
> +-------
> +There are a total of 480 interrupt sources in AST2700. Due to the limitation of
> +interrupt numbers of processors, the interrupts are merged every 32 sources for
> +interrupt numbers greater than 127.
> +
> +There are two levels of interrupt controllers, INTC (CPU Die) and INTCIO
> +(I/O Die).
> +
> +Interrupt Mapping
> +-----------------
> +- INTC: Handles interrupt sources 0 - 127 and integrates signals from INTCIO.
> +- INTCIO: Handles interrupt sources 128 - 319 independently.
> +
> +QEMU Support
> +------------
> +Currently, only GIC 192 to 201 are supported, and their source interrupts are
> +from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
> +GIC 192-201.
> +
> +Design for GICINT 196
> +---------------------
> +The orgate has interrupt sources ranging from 0 to 31, with its output pin
> +connected to INTCIO "T0 GICINT_196". The output pin is then connected to INTC
> +"GIC_192_201" at bit 4, and its bit 4 output pin is connected to GIC 196.
> +
> +INTC GIC_192_201 Output Pin Mapping
> +-----------------------------------
> +The design of INTC GIC_192_201 have 10 output pins, mapped as following:
> +
> +==== ====
> +Bit GIC
> +==== ====
> +0 192
> +1 193
> +2 194
> +3 195
> +4 196
> +5 197
> +6 198
> +7 199
> +8 200
> +9 201
> +==== ====
> +
> +AST2700 A0
> +----------
> +It has only one INTC controller, and currently, only GIC 128-136 is supported.
> +To support both AST2700 A1 and AST2700 A0, there are 10 OR gates in the INTC,
> +with gates 1 to 9 supporting GIC 128-136.
> +
> +Design for GICINT 132
> +---------------------
> +The orgate has interrupt sources ranging from 0 to 31, with its output pin
> +connected to INTC. The output pin is then connected to GIC 132.
> +
> +Block Diagram of GICINT 196 for AST2700 A1 and GICINT 132 for AST2700 A0
> +------------------------------------------------------------------------
> +
> +.. code-block::
> +
> + |-------------------------------------------------------------------------------------------------------|
> + | AST2700 A1 Design |
> + | To GICINT196 |
> + | |
> + | ETH1 |-----------| |--------------------------| |--------------| |
> + | -------->|0 | | INTCIO | | orgates[0] | |
> + | ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
> + | -------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
> + | ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
> + | -------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
> + | UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 | | |
> + | -------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
> + | UART1 | 22| orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
> + | -------->|8 23| orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
> + | UART2 | 24| orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
> + | -------->|9 25| orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
> + | UART3 | 26| |--------------------------| |--------------| | |
> + | ---------|10 27| | |
> + | UART5 | 28| | |
> + | -------->|11 29| | |
> + | UART6 | | | |
> + | -------->|12 30| |-----------------------------------------------------------------------| |
> + | UART7 | 31| | |
> + | -------->|13 | | |
> + | UART8 | OR[0:31] | | |------------------------------| |----------| |
> + | -------->|14 | | | INTC | | GIC | |
> + | UART9 | | | |inpin[0:0]--------->outpin[0] |---------->|192 | |
> + | -------->|15 | | |inpin[0:1]--------->outpin[1] |---------->|193 | |
> + | UART10 | | | |inpin[0:2]--------->outpin[2] |---------->|194 | |
> + | -------->|16 | | |inpin[0:3]--------->outpin[3] |---------->|195 | |
> + | UART11 | | |--------------> |inpin[0:4]--------->outpin[4] |---------->|196 | |
> + | -------->|17 | |inpin[0:5]--------->outpin[5] |---------->|197 | |
> + | UART12 | | |inpin[0:6]--------->outpin[6] |---------->|198 | |
> + | -------->|18 | |inpin[0:7]--------->outpin[7] |---------->|199 | |
> + | |-----------| |inpin[0:8]--------->outpin[8] |---------->|200 | |
> + | |inpin[0:9]--------->outpin[9] |---------->|201 | |
> + |-------------------------------------------------------------------------------------------------------|
> + |-------------------------------------------------------------------------------------------------------|
> + | ETH1 |-----------| orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | |
> + | -------->|0 | orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | |
> + | ETH2 | 4| orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | |
> + | -------->|1 5| orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | |
> + | ETH3 | 6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132 | |
> + | -------->|2 19| orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | |
> + | UART0 | 20| orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | |
> + | -------->|7 21| orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | |
> + | UART1 | 22| orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | |
> + | -------->|8 23| |------------------------------| |----------| |
> + | UART2 | 24| |
> + | -------->|9 25| AST2700 A0 Design |
> + | UART3 | 26| |
> + | -------->|10 27| |
> + | UART5 | 28| |
> + | -------->|11 29| GICINT132 |
> + | UART6 | | |
> + | -------->|12 30| |
> + | UART7 | 31| |
> + | -------->|13 | |
> + | UART8 | OR[0:31] | |
> + | -------->|14 | |
> + | UART9 | | |
> + | -------->|15 | |
> + | UART10 | | |
> + | -------->|16 | |
> + | UART11 | | |
> + | -------->|17 | |
> + | UART12 | | |
> + | -------->|18 | |
> + | |-----------| |
> + | |
> + |-------------------------------------------------------------------------------------------------------|
> diff --git a/docs/specs/index.rst b/docs/specs/index.rst
> index d7675cebc2..f19d73c9f6 100644
> --- a/docs/specs/index.rst
> +++ b/docs/specs/index.rst
> @@ -38,3 +38,4 @@ guest hardware that is specific to QEMU.
> rocker
> riscv-iommu
> riscv-aia
> + aspeed-intc
prev parent reply other threads:[~2025-03-04 7:27 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 9:54 [PATCH v4 00/23] Support AST2700 A1 Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 01/23] hw/intc/aspeed: Support setting different memory size Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 02/23] hw/intc/aspeed: Support setting different register sizes Jamin Lin via
2025-03-03 13:54 ` Cédric Le Goater
2025-03-04 10:03 ` Jamin Lin
2025-03-04 10:43 ` Cédric Le Goater
2025-03-03 9:54 ` [PATCH v4 03/23] hw/intc/aspeed: Reduce regs array size by adding a register sub-region Jamin Lin via
2025-03-03 14:21 ` Cédric Le Goater
2025-03-05 4:05 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 04/23] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 05/23] hw/intc/aspeed: Add object type name to trace events for better debugging Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 06/23] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-03-03 14:23 ` Cédric Le Goater
2025-03-04 2:55 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 07/23] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 08/23] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 09/23] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 10/23] hw/intc/aspeed: Add support for multiple output pins in INTC Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 11/23] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 12/23] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-03-04 6:52 ` Cédric Le Goater
2025-03-05 5:24 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 13/23] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 14/23] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-03-04 7:21 ` Cédric Le Goater
2025-03-06 2:26 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 15/23] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Jamin Lin via
2025-03-04 7:08 ` Cédric Le Goater
2025-03-03 9:54 ` [PATCH v4 16/23] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-03-03 9:54 ` [PATCH v4 17/23] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Jamin Lin via
2025-03-04 7:12 ` Cédric Le Goater
2025-03-06 6:32 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 18/23] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-03-04 7:17 ` Cédric Le Goater
2025-03-06 8:29 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 19/23] hw/arm/aspeed: Add SoC and Machine Support " Jamin Lin via
2025-03-03 17:41 ` Cédric Le Goater
2025-03-04 5:30 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 20/23] tests/functional/aspeed: Introduce start_ast2700_test API and update hwmon path Jamin Lin via
2025-03-03 16:47 ` Cédric Le Goater
2025-03-04 3:33 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 21/23] tests/functional/aspeed: Update test ASPEED SDK v09.05 Jamin Lin via
2025-03-03 16:50 ` Cédric Le Goater
2025-03-04 3:48 ` Jamin Lin
2025-03-03 9:54 ` [PATCH v4 22/23] tests/functional/aspeed: Add test case for AST2700 A1 Jamin Lin via
2025-03-03 16:50 ` Cédric Le Goater
2025-03-03 9:54 ` [PATCH v4 23/23] docs/specs: Add aspeed-intc Jamin Lin via
2025-03-04 7:26 ` Cédric Le Goater [this message]
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