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[149.14.88.106]) by smtp.gmail.com with ESMTPSA id y5-20020a1c4b05000000b0040303a9965asm1382313wma.40.2023.09.13.01.50.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Sep 2023 01:50:07 -0700 (PDT) Message-ID: Date: Wed, 13 Sep 2023 10:50:06 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , Ilya Leoshkevich , David Hildenbrand References: <20230905115000.53587-1-thuth@redhat.com> <20230905115000.53587-2-thuth@redhat.com> From: Thomas Huth Subject: Re: [risu PATCH v2 1/4] s390x: Add basic s390x support to the C code In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/09/2023 18.50, Peter Maydell wrote: > On Tue, 5 Sept 2023 at 12:50, Thomas Huth wrote: >> >> With these changes, it is now possible to compile the "risu" binary >> for s390x hosts. >> >> Acked-by: Ilya Leoshkevich >> Signed-off-by: Thomas Huth > > > >> +/* reginfo_init: initialize with a ucontext */ >> +void reginfo_init(struct reginfo *ri, ucontext_t *uc) >> +{ >> + int i; >> + >> + memset(ri, 0, sizeof(*ri)); >> + >> + ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.psw.addr); > > Here we extract the faulting instruction, assuming it to > be a 32-bit insn starting at uc_mcontext.psw.addr... > >> + ri->psw_mask = uc->uc_mcontext.psw.mask; >> + ri->psw_addr = uc->uc_mcontext.psw.addr - image_start_address; >> + >> + for (i = 0; i < 16; i++) { >> + ri->gregs[i] = uc->uc_mcontext.gregs[i]; >> + } >> + >> + memcpy(&ri->fpregs, &uc->uc_mcontext.fpregs, sizeof(fpregset_t)); >> +} > >> +void advance_pc(void *vuc) >> +{ >> + /* >> + * Note: The PSW address already points to the next instruction >> + * after we get a SIGILL, so we must not advance it here! >> + */ >> + // ucontext_t *uc = (ucontext_t *) vuc; >> + // uc->uc_mcontext.psw.addr += 4; > > ...but here we say that psw.addr points to the instruction > *after* the faulting one. > > These don't seem like they can both be correct? Drat, you're right, thanks for the hint! The code in reginfo_init() is wrong, it takes the instruction after the illegal one. It was just working (wrongly, but without crashing) by accident here since the OP_TESTEND instruction was preceeded by an OP_COMPARE instruction :-/ To get the address (and thus opcode) of the faulting instruction, I have to use siginfo_t->si_addr instead of using the ucontext_t structure. I will fix it in the next version. Thomas