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Mon, 01 Sep 2025 21:06:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpOtBZ0dikytCyzkLuSCErI+4iPOCDsOIiHOk43PNNuH6P2naqBFHAgQYWpn9GtzeTiijmxw== X-Received: by 2002:a17:902:dac6:b0:249:789:28f0 with SMTP id d9443c01a7336-249448cc423mr116060005ad.13.1756785968500; Mon, 01 Sep 2025 21:06:08 -0700 (PDT) Received: from [172.19.248.181] ([80.149.170.9]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24903727e23sm119538555ad.45.2025.09.01.21.05.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Sep 2025 21:06:08 -0700 (PDT) Message-ID: Date: Mon, 1 Sep 2025 20:33:22 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 04/39] target/hexagon: Implement start/stop helpers To: ltaylorsimpson@gmail.com, qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, philmd@linaro.org, quic_mathbern@quicinc.com, ale@rev.ng, anjo@rev.ng, quic_mliebel@quicinc.com, alex.bennee@linaro.org, quic_mburton@quicinc.com, sidneym@quicinc.com, 'Brian Cain' References: <20250301052845.1012069-1-brian.cain@oss.qualcomm.com> <20250301052845.1012069-5-brian.cain@oss.qualcomm.com> <016801db975a$a42bdb30$ec839190$@gmail.com> Content-Language: en-US From: Brian Cain In-Reply-To: <016801db975a$a42bdb30$ec839190$@gmail.com> Content-Type: text/plain; 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envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/17/2025 11:35 AM, ltaylorsimpson@gmail.com wrote: > >> -----Original Message----- >> From: Brian Cain >> Sent: Friday, February 28, 2025 11:28 PM >> To: qemu-devel@nongnu.org >> Cc: brian.cain@oss.qualcomm.com; richard.henderson@linaro.org; >> philmd@linaro.org; quic_mathbern@quicinc.com; ale@rev.ng; anjo@rev.ng; >> quic_mliebel@quicinc.com; ltaylorsimpson@gmail.com; >> alex.bennee@linaro.org; quic_mburton@quicinc.com; >> sidneym@quicinc.com; Brian Cain >> Subject: [PATCH 04/39] target/hexagon: Implement start/stop helpers >> >> From: Brian Cain >> >> Signed-off-by: Brian Cain >> --- >> target/hexagon/cpu.h | 3 ++ >> target/hexagon/cpu_bits.h | 1 + >> target/hexagon/cpu_helper.h | 3 ++ >> target/hexagon/cpu.c | 14 +++++- >> target/hexagon/cpu_helper.c | 94 >> +++++++++++++++++++++++++++++++++++++ >> target/hexagon/op_helper.c | 4 +- >> 6 files changed, 116 insertions(+), 3 deletions(-) >> >> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index >> 894219fd20..1549c4f1f0 100644 >> --- a/target/hexagon/cpu.h >> +++ b/target/hexagon/cpu.h >> @@ -41,6 +41,7 @@ typedef struct CPUHexagonTLBContext >> CPUHexagonTLBContext; #define REG_WRITES_MAX 32 >> #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ >> #define VSTORES_MAX 2 >> +#define VECTOR_UNIT_MAX 8 > Not related to start/stop and not used in this patch. HVX contexts moved out of this series, they'll return in a new series after we land parts 1,2,3. > >> #ifndef CONFIG_USER_ONLY >> #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0 >> @@ -178,6 +179,7 @@ struct ArchCPU { >> #ifndef CONFIG_USER_ONLY >> uint32_t num_tlbs; >> uint32_t l2vic_base_addr; >> + uint32_t hvx_contexts; > Not related to start/stop. > >> #endif >> }; >> >> @@ -194,6 +196,7 @@ G_NORETURN void >> hexagon_raise_exception_err(CPUHexagonState *env, uint32_t >> hexagon_greg_read(CPUHexagonState *env, uint32_t reg); uint32_t >> hexagon_sreg_read(CPUHexagonState *env, uint32_t reg); void >> hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t >> val); >> +void hexagon_cpu_soft_reset(CPUHexagonState *env); >> #endif >> >> #include "exec/cpu-all.h" >> diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index >> b559a7ba88..610094a759 100644 >> --- a/target/hexagon/cpu_bits.h >> +++ b/target/hexagon/cpu_bits.h >> @@ -52,6 +52,7 @@ enum hex_event { >> >> enum hex_cause { >> HEX_CAUSE_NONE = -1, >> + HEX_CAUSE_RESET = 0x000, >> HEX_CAUSE_TRAP0 = 0x172, >> HEX_CAUSE_FETCH_NO_UPAGE = 0x012, >> HEX_CAUSE_INVALID_PACKET = 0x015, >> diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h >> index 6f0c6697ad..95a0cc0788 100644 >> --- a/target/hexagon/cpu_helper.h >> +++ b/target/hexagon/cpu_helper.h >> @@ -17,6 +17,9 @@ void >> hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t); >> void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t >> old); int get_exe_mode(CPUHexagonState *env); void >> clear_wait_mode(CPUHexagonState *env); >> +void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause); void >> +hexagon_start_threads(CPUHexagonState *env, uint32_t mask); void >> +hexagon_stop_thread(CPUHexagonState *env); >> >> static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t reg, >> uint32_t val) diff --git a/target/hexagon/cpu.c >> b/target/hexagon/cpu.c index cb56b929cf..84a96a194b 100644 >> --- a/target/hexagon/cpu.c >> +++ b/target/hexagon/cpu.c >> @@ -32,6 +32,7 @@ >> >> #ifndef CONFIG_USER_ONLY >> #include "sys_macros.h" >> +#include "qemu/main-loop.h" >> #endif >> >> static void hexagon_v66_cpu_init(Object *obj) { } @@ -61,6 +62,7 @@ static >> const Property hexagon_cpu_properties[] = { >> DEFINE_PROP_UINT32("jtlb-entries", HexagonCPU, num_tlbs, >> MAX_TLB_ENTRIES), >> DEFINE_PROP_UINT32("l2vic-base-addr", HexagonCPU, l2vic_base_addr, >> 0xffffffffULL), >> + DEFINE_PROP_UINT32("hvx-contexts", HexagonCPU, hvx_contexts, 0), > Not related to start/stop. > >> #endif >> DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),