* [Qemu-devel] [PATCH v3 1/2] exec: [tcg] Track which vCPU is performing translation and execution
2016-05-18 10:47 [Qemu-devel] [PATCH v3 0/2] trace: Add event for vCPU memory accesses Lluís Vilanova
@ 2016-05-18 10:47 ` Lluís Vilanova
2016-05-18 17:54 ` Richard Henderson
2016-05-18 10:47 ` [Qemu-devel] [PATCH v3 2/2] trace: [all] Add "guest_mem_before" event Lluís Vilanova
1 sibling, 1 reply; 7+ messages in thread
From: Lluís Vilanova @ 2016-05-18 10:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Richard Henderson,
Edgar E. Iglesias, Paolo Bonzini, Eduardo Habkost, Michael Walle,
Aurelien Jarno, Leon Alrae, Anthony Green, Jia Liu,
Alexander Graf, Blue Swirl, Mark Cave-Ayland, Bastian Koppelmann,
Guan Xuetao, Max Filippov, Peter Crosthwaite, open list:ARM,
open list:PowerPC
Information is tracked inside the TCGContext structure, and later used
by tracing events with the 'tcg' and 'vcpu' properties.
The 'cpu' field is used to check tracing of translation-time
events ("*_trans"). The 'tcg_env' field is used to pass it to
execution-time events ("*_exec").
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target-alpha/translate.c | 1 +
target-arm/translate.c | 1 +
target-cris/translate.c | 1 +
target-cris/translate_v10.c | 1 +
target-i386/translate.c | 1 +
target-lm32/translate.c | 1 +
target-m68k/translate.c | 1 +
target-microblaze/translate.c | 1 +
target-mips/translate.c | 1 +
target-moxie/translate.c | 1 +
target-openrisc/translate.c | 1 +
target-ppc/translate.c | 1 +
target-s390x/translate.c | 1 +
target-sh4/translate.c | 1 +
target-sparc/translate.c | 1 +
target-tilegx/translate.c | 1 +
target-tricore/translate.c | 1 +
target-unicore32/translate.c | 1 +
target-xtensa/translate.c | 1 +
tcg/tcg.h | 4 ++++
translate-all.c | 2 ++
21 files changed, 25 insertions(+)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5b86992..67681f6 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -150,6 +150,7 @@ void alpha_translate_init(void)
done_init = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 31; i++) {
cpu_std_ir[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 940ec8d..1a7496b 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -84,6 +84,7 @@ void arm_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 16; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index a73176c..f603af3 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3364,6 +3364,7 @@ void cris_initialize_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 7607ead..f2e9768 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1250,6 +1250,7 @@ void cris_initialize_crisv10_tcg(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cc_x = tcg_global_mem_new(cpu_env,
offsetof(CPUCRISState, cc_x), "cc_x");
cc_src = tcg_global_mem_new(cpu_env,
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1a1214d..7a6ef7c 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8135,6 +8135,7 @@ void tcg_x86_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_cc_op = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUX86State, cc_op), "cc_op");
cpu_cc_dst = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_dst),
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 256a51f..b2e5a3e 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1191,6 +1191,7 @@ void lm32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 7560c3a..f90f80e 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -77,6 +77,7 @@ void m68k_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
#define DEFO32(name, offset) \
QREG_##name = tcg_global_mem_new_i32(cpu_env, \
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index f944965..05092f1 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1869,6 +1869,7 @@ void mb_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
env_debug = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, debug),
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a3a05ec..24f994c 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19993,6 +19993,7 @@ void mips_tcg_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
TCGV_UNUSED(cpu_gpr[0]);
for (i = 1; i < 32; i++)
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index a437e2a..44c8c0d 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -106,6 +106,7 @@ void moxie_translate_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMoxieState, pc), "$pc");
for (i = 0; i < 16; i++)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 5d0ab44..170bb40 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -78,6 +78,7 @@ void openrisc_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
env_flags = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b3860ec..cf4771b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -87,6 +87,7 @@ void ppc_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
p = cpu_reg_names;
cpu_reg_names_size = sizeof(cpu_reg_names);
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index c871ef2..24c1d07 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -168,6 +168,7 @@ void s390x_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
psw_addr = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUS390XState, psw.addr),
"psw_addr");
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 7c18968..b838386 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -100,6 +100,7 @@ void sh4_translate_init(void)
return;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 24; i++)
cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 7998ff5..f12b878 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5392,6 +5392,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
inited = 1;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_regwptr = tcg_global_mem_new_ptr(cpu_env,
offsetof(CPUSPARCState, regwptr),
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 03918eb..399843a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2442,6 +2442,7 @@ void tilegx_tcg_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i64(cpu_env, offsetof(CPUTLGState, pc), "pc");
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_regs[i] = tcg_global_mem_new_i64(cpu_env,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 912bf22..7195c4e 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -8823,6 +8823,7 @@ void tricore_tcg_init(void)
return;
}
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
/* reg init */
for (i = 0 ; i < 16 ; i++) {
cpu_gpr_a[i] = tcg_global_mem_new(cpu_env,
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 39af3af..d2b786e 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -69,6 +69,7 @@ void uc32_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 9894488..0ba59da 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -218,6 +218,7 @@ void xtensa_translate_init(void)
int i;
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ tcg_ctx.tcg_env = cpu_env;
cpu_pc = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUXtensaState, pc), "pc");
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 40c8fbe..89914c2 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -576,6 +576,10 @@ struct TCGContext {
TBContext tb_ctx;
+ /* Track which vCPU triggers events */
+ CPUState *cpu; /* *_trans */
+ TCGv_env tcg_env; /* *_exec */
+
/* The TCGBackendData structure is private to tcg-target.inc.c. */
struct TCGBackendData *be;
diff --git a/translate-all.c b/translate-all.c
index 8329ea6..360b26a 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1094,7 +1094,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
+ tcg_ctx.cpu = ENV_GET_CPU(env);
gen_intermediate_code(env, tb);
+ tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);
^ permalink raw reply related [flat|nested] 7+ messages in thread* [Qemu-devel] [PATCH v3 2/2] trace: [all] Add "guest_mem_before" event
2016-05-18 10:47 [Qemu-devel] [PATCH v3 0/2] trace: Add event for vCPU memory accesses Lluís Vilanova
2016-05-18 10:47 ` [Qemu-devel] [PATCH v3 1/2] exec: [tcg] Track which vCPU is performing translation and execution Lluís Vilanova
@ 2016-05-18 10:47 ` Lluís Vilanova
2016-05-18 17:53 ` Richard Henderson
1 sibling, 1 reply; 7+ messages in thread
From: Lluís Vilanova @ 2016-05-18 10:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefan Hajnoczi, Paolo Bonzini, Peter Crosthwaite,
Richard Henderson
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
include/exec/cpu_ldst_template.h | 25 ++++++++++++++++
include/exec/cpu_ldst_useronly_template.h | 22 ++++++++++++++
tcg/tcg-op.c | 32 ++++++++++++++++++--
trace-events | 22 ++++++++++++++
trace/mem-internal.h | 46 +++++++++++++++++++++++++++++
trace/mem.h | 34 +++++++++++++++++++++
6 files changed, 177 insertions(+), 4 deletions(-)
create mode 100644 trace/mem-internal.h
create mode 100644 trace/mem.h
diff --git a/include/exec/cpu_ldst_template.h b/include/exec/cpu_ldst_template.h
index 3091c00..eaf69a1 100644
--- a/include/exec/cpu_ldst_template.h
+++ b/include/exec/cpu_ldst_template.h
@@ -23,6 +23,13 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#if !defined(SOFTMMU_CODE_ACCESS)
+#include "trace.h"
+#endif
+
+#include "trace/mem.h"
+
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
@@ -80,6 +87,12 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
int mmu_idx;
TCGMemOpIdx oi;
+#if !defined(SOFTMMU_CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(SHIFT, false, MO_TE, false));
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
@@ -112,6 +125,12 @@ glue(glue(glue(cpu_lds, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
int mmu_idx;
TCGMemOpIdx oi;
+#if !defined(SOFTMMU_CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(SHIFT, true, MO_TE, false));
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
@@ -148,6 +167,12 @@ glue(glue(glue(cpu_st, SUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
int mmu_idx;
TCGMemOpIdx oi;
+#if !defined(SOFTMMU_CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(SHIFT, false, MO_TE, true));
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
diff --git a/include/exec/cpu_ldst_useronly_template.h b/include/exec/cpu_ldst_useronly_template.h
index 040b147..b1378bf 100644
--- a/include/exec/cpu_ldst_useronly_template.h
+++ b/include/exec/cpu_ldst_useronly_template.h
@@ -22,6 +22,13 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#if !defined(CODE_ACCESS)
+#include "trace.h"
+#endif
+
+#include "trace/mem.h"
+
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
@@ -53,6 +60,11 @@
static inline RES_TYPE
glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
{
+#if !defined(CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(DATA_SIZE, false, MO_TE, false));
+#endif
return glue(glue(ld, USUFFIX), _p)(g2h(ptr));
}
@@ -68,6 +80,11 @@ glue(glue(glue(cpu_ld, USUFFIX), MEMSUFFIX), _ra)(CPUArchState *env,
static inline int
glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr)
{
+#if !defined(CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(DATA_SIZE, true, MO_TE, false));
+#endif
return glue(glue(lds, SUFFIX), _p)(g2h(ptr));
}
@@ -85,6 +102,11 @@ static inline void
glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr,
RES_TYPE v)
{
+#if !defined(CODE_ACCESS)
+ trace_guest_mem_before_exec(
+ ENV_GET_CPU(env), ptr,
+ trace_mem_build_info(DATA_SIZE, false, MO_TE, true));
+#endif
glue(glue(st, SUFFIX), _p)(g2h(ptr), v);
}
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index f554b86..3b7e3ff 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -25,6 +25,8 @@
#include "qemu/osdep.h"
#include "tcg.h"
#include "tcg-op.h"
+#include "trace-tcg.h"
+#include "trace/mem.h"
/* Reduce the number of ifdefs below. This assumes that all uses of
TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
@@ -1904,22 +1906,41 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
#endif
}
-void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+static inline void do_tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx,
+ TCGMemOp memop)
{
memop = tcg_canonicalize_memop(memop, 0, 0);
gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx);
}
-void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+{
+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ addr, trace_mem_get_info(memop, 0));
+ do_tcg_gen_qemu_ld_i32(val, addr, idx, memop);
+}
+
+static inline void do_tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx,
+ TCGMemOp memop)
{
memop = tcg_canonicalize_memop(memop, 0, 1);
gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx);
}
+void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
+{
+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ addr, trace_mem_get_info(memop, 1));
+ do_tcg_gen_qemu_st_i32(val, addr, idx, memop);
+}
+
void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ addr, trace_mem_get_info(memop, 0));
+
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
- tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
+ do_tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop);
if (memop & MO_SIGN) {
tcg_gen_sari_i32(TCGV_HIGH(val), TCGV_LOW(val), 31);
} else {
@@ -1934,8 +1955,11 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
+ trace_guest_mem_before_tcg(tcg_ctx.cpu, tcg_ctx.tcg_env,
+ addr, trace_mem_get_info(memop, 0));
+
if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) {
- tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
+ do_tcg_gen_qemu_st_i32(TCGV_LOW(val), addr, idx, memop);
return;
}
diff --git a/trace-events b/trace-events
index 8350743..399cf9d 100644
--- a/trace-events
+++ b/trace-events
@@ -1909,3 +1909,25 @@ aspeed_vic_update_fiq(int flags) "Raising FIQ: %d"
aspeed_vic_update_irq(int flags) "Raising IRQ: %d"
aspeed_vic_read(uint64_t offset, unsigned size, uint32_t value) "From 0x%" PRIx64 " of size %u: 0x%" PRIx32
aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
+
+
+### Guest events, keep at bottom
+
+# @vaddr: Access' virtual address.
+# @info : Access' information (see below).
+#
+# Start virtual memory access (before any potential access violation).
+#
+# Does not include memory accesses performed by devices.
+#
+# Access information can be parsed as:
+#
+# struct mem_info {
+# uint8_t size_shift : 2; /* interpreted as "1 << size_shift" bytes */
+# bool sign_extend: 1; /* sign-extended */
+# uint8_t endianness : 1; /* 0: little, 1: big */
+# bool store : 1; /* wheter it's a store operation */
+# };
+#
+# Targets: TCG(all)
+disable vcpu tcg guest_mem_before(TCGv vaddr, uint8_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d"
diff --git a/trace/mem-internal.h b/trace/mem-internal.h
new file mode 100644
index 0000000..d575bb3
--- /dev/null
+++ b/trace/mem-internal.h
@@ -0,0 +1,46 @@
+/*
+ * Helper functions for guest memory tracing
+ *
+ * Copyright (C) 2016 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TRACE__MEM_INTERNAL_H
+#define TRACE__MEM_INTERNAL_H
+
+static inline uint8_t trace_mem_get_info(TCGMemOp op, bool store)
+{
+ uint8_t res = op;
+ bool be = (op & MO_BSWAP) == MO_BE;
+
+ /* remove untraced fields */
+ res &= (1ULL << 4) - 1;
+ /* make endianness absolute */
+ res &= ~MO_BSWAP;
+ if (be) {
+ res |= 1ULL << 3;
+ }
+ /* add fields */
+ if (store) {
+ res |= 1ULL << 4;
+ }
+
+ return res;
+}
+
+static inline inline uint8_t trace_mem_build_info(
+ TCGMemOp size, bool sign_extend, TCGMemOp endianness, bool store)
+{
+ uint8_t res = 0;
+ res |= size;
+ res |= (sign_extend << 2);
+ if (endianness == MO_BE) {
+ res |= (1ULL << 3);
+ }
+ res |= (store << 4);
+ return res;
+}
+
+#endif /* TRACE__MEM_INTERNAL_H */
diff --git a/trace/mem.h b/trace/mem.h
new file mode 100644
index 0000000..c76a572
--- /dev/null
+++ b/trace/mem.h
@@ -0,0 +1,34 @@
+/*
+ * Helper functions for guest memory tracing
+ *
+ * Copyright (C) 2016 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef TRACE__MEM_H
+#define TRACE__MEM_H
+
+#include "tcg/tcg.h"
+
+
+/**
+ * trace_mem_get_info:
+ *
+ * Return a value for the 'info' argument in guest memory access traces.
+ */
+static uint8_t trace_mem_get_info(TCGMemOp op, bool store);
+
+/**
+ * trace_mem_build_info:
+ *
+ * Return a value for the 'info' argument in guest memory access traces.
+ */
+static uint8_t trace_mem_build_info(TCGMemOp size, bool sign_extend,
+ TCGMemOp endianness, bool store);
+
+
+#include "trace/mem-internal.h"
+
+#endif /* TRACE__MEM_H */
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