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From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
	Daniel Henrique Barboza <danielhb413@gmail.com>,
	David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH 01/13] ppc: Drop support for POWER9 and POWER10 DD1 chips
Date: Tue, 12 Mar 2024 10:25:03 +0530	[thread overview]
Message-ID: <d1b34bf3-e9b7-48e6-9e46-ec396068b888@linux.ibm.com> (raw)
In-Reply-To: <5f8b269f-1f43-42ab-b4bf-d0314b739493@linux.ibm.com>



On 3/12/24 10:20, Harsh Prateek Bora wrote:
> 
> 
> On 3/12/24 00:21, Nicholas Piggin wrote:
>> The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
>> any use in QEMU. Remove them.
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>>   hw/ppc/spapr_cpu_core.c |  2 --
>>   target/ppc/cpu-models.c |  4 ----
>>   target/ppc/cpu_init.c   |  7 ++-----
>>   target/ppc/kvm.c        | 11 -----------
>>   4 files changed, 2 insertions(+), 22 deletions(-)
> 
> Do we want to squash in removal of the macro as well?
>

<snip>
Actually both, correcting diff:

diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index 0229ef3a9a..7d89b41214 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -348,11 +348,9 @@ enum {
      CPU_POWERPC_POWER8NVL_BASE     = 0x004C0000,
      CPU_POWERPC_POWER8NVL_v10      = 0x004C0100,
      CPU_POWERPC_POWER9_BASE        = 0x004E0000,
-    CPU_POWERPC_POWER9_DD1         = 0x004E1100,
      CPU_POWERPC_POWER9_DD20        = 0x004E1200,
      CPU_POWERPC_POWER9_DD22        = 0x004E1202,
      CPU_POWERPC_POWER10_BASE       = 0x00800000,
-    CPU_POWERPC_POWER10_DD1        = 0x00801100,
      CPU_POWERPC_POWER10_DD20       = 0x00801200,
      CPU_POWERPC_970_v22            = 0x00390202,
      CPU_POWERPC_970FX_v10          = 0x00391100,

> 
> With that,
> 
> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> 
> regards,
> Harsh
> 
>>
>> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
>> index 40b7c52f7f..50523ead25 100644
>> --- a/hw/ppc/spapr_cpu_core.c
>> +++ b/hw/ppc/spapr_cpu_core.c
>> @@ -394,10 +394,8 @@ static const TypeInfo spapr_cpu_core_type_infos[] 
>> = {
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
>> -    DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.2"),
>> -    DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
>>       DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
>>   #ifdef CONFIG_KVM
>>       DEFINE_SPAPR_CPU_CORE_TYPE("host"),
>> diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
>> index 36e465b390..f2301b43f7 100644
>> --- a/target/ppc/cpu-models.c
>> +++ b/target/ppc/cpu-models.c
>> @@ -728,14 +728,10 @@
>>                   "POWER8 v2.0")
>>       POWERPC_DEF("power8nvl_v1.0", CPU_POWERPC_POWER8NVL_v10,         
>> POWER8,
>>                   "POWER8NVL v1.0")
>> -    POWERPC_DEF("power9_v1.0",   CPU_POWERPC_POWER9_DD1,             
>> POWER9,
>> -                "POWER9 v1.0")
>>       POWERPC_DEF("power9_v2.0",   CPU_POWERPC_POWER9_DD20,            
>> POWER9,
>>                   "POWER9 v2.0")
>>       POWERPC_DEF("power9_v2.2",   CPU_POWERPC_POWER9_DD22,            
>> POWER9,
>>                   "POWER9 v2.2")
>> -    POWERPC_DEF("power10_v1.0",  CPU_POWERPC_POWER10_DD1,            
>> POWER10,
>> -                "POWER10 v1.0")
>>       POWERPC_DEF("power10_v2.0",  CPU_POWERPC_POWER10_DD20,           
>> POWER10,
>>                   "POWER10 v2.0")
>>   #endif /* defined (TARGET_PPC64) */
>> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
>> index 1d3d1db7c3..572cbdf25f 100644
>> --- a/target/ppc/cpu_init.c
>> +++ b/target/ppc/cpu_init.c
>> @@ -6350,10 +6350,7 @@ static bool 
>> ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
>>           return false;
>>       }
>> -    if ((pvr & 0x0f00) == 0x100) {
>> -        /* DD1.x always matches power9_v1.0 */
>> -        return true;
>> -    } else if ((pvr & 0x0f00) == 0x200) {
>> +    if ((pvr & 0x0f00) == 0x200) {
>>           if ((pvr & 0xf) < 2) {
>>               /* DD2.0, DD2.1 match power9_v2.0 */
>>               if ((pcc->pvr & 0xf) == 0) {
>> @@ -6536,7 +6533,7 @@ static bool 
>> ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
>>       }
>>       if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
>> -        /* Major DD version matches to power10_v1.0 and power10_v2.0 */
>> +        /* Major DD version matches power10_v2.0 */
>>           return true;
>>       }
>> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
>> index bcf30a5400..525fbe3892 100644
>> --- a/target/ppc/kvm.c
>> +++ b/target/ppc/kvm.c
>> @@ -2369,17 +2369,6 @@ static void 
>> kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
>>   #if defined(TARGET_PPC64)
>>       pcc->radix_page_info = kvmppc_get_radix_page_info();
>> -
>> -    if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
>> -        /*
>> -         * POWER9 DD1 has some bugs which make it not really ISA 3.00
>> -         * compliant.  More importantly, advertising ISA 3.00
>> -         * architected mode may prevent guests from activating
>> -         * necessary DD1 workarounds.
>> -         */
>> -        pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
>> -                                | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
>> -    }
>>   #endif /* defined(TARGET_PPC64) */
>>   }
> 


  reply	other threads:[~2024-03-12  4:56 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-11 18:51 [PATCH 00/13] misc ppc patches Nicholas Piggin
2024-03-11 18:51 ` [PATCH 01/13] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
2024-03-12  4:50   ` Harsh Prateek Bora
2024-03-12  4:55     ` Harsh Prateek Bora [this message]
2024-03-12  8:59       ` Nicholas Piggin
2024-03-12  9:06         ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 02/13] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-03-12  8:10   ` Harsh Prateek Bora
2024-03-12  8:55     ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 03/13] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
2024-03-12  8:40   ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 04/13] ppc/spapr: Remove copy-paste " Nicholas Piggin
2024-03-12  8:49   ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 05/13] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-03-12  9:13   ` Harsh Prateek Bora
2024-03-11 18:51 ` [PATCH 06/13] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-03-11 20:05   ` Philippe Mathieu-Daudé
2024-03-11 21:07     ` BALATON Zoltan
2024-03-12  4:50       ` Nicholas Piggin
2024-03-12  9:59         ` BALATON Zoltan
2024-03-12 10:33           ` Nicholas Piggin
2024-03-12  4:45     ` Nicholas Piggin
2024-03-12  9:34   ` Harsh Prateek Bora
2024-03-12 10:34     ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 07/13] ppc/pnv: Permit ibm, pa-features set per machine variant Nicholas Piggin
2024-03-12  8:02   ` [PATCH 07/13] ppc/pnv: Permit ibm,pa-features " Cédric Le Goater
2024-03-11 18:51 ` [PATCH 08/13] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-03-12  8:06   ` Cédric Le Goater
2024-03-12  8:54     ` Nicholas Piggin
2024-03-12  9:14       ` Cédric Le Goater
2024-03-11 18:51 ` [PATCH 09/13] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-03-12 10:27   ` Harsh Prateek Bora
2024-03-12 10:33     ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 10/13] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
2024-03-12 10:03   ` Harsh Prateek Bora
2024-03-12 10:34     ` Nicholas Piggin
2024-03-11 18:51 ` [PATCH 11/13] target/ppc: Make checkstop actually stop the system Nicholas Piggin
2024-03-11 18:51 ` [PATCH 12/13] target/ppc: improve checkstop logging Nicholas Piggin
2024-03-11 18:51 ` [PATCH 13/13] target/ppc: Implement attn instruction on BookS 64-bit processors Nicholas Piggin
2024-03-11 20:06 ` [PATCH 00/13] misc ppc patches Philippe Mathieu-Daudé

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