* [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes
@ 2018-10-16 12:14 Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE Aleksandar Markovic
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Aleksandar Markovic @ 2018-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, jancraig, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
This series adds opcodes and accompanying comments for Ingenic's
MXU ASE.
Aleksandar Markovic (4):
target/mips: Add basic description of MXU ASE
target/mips: Add assembler mnemonics list for MXU ASE
target/mips: Add organizational chart of MXU ASE
target/mips: Add opcode values of MXU ASE
target/mips/translate.c | 540 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 540 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE
2018-10-16 12:14 [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes Aleksandar Markovic
@ 2018-10-16 12:14 ` Aleksandar Markovic
2018-10-16 13:27 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for " Aleksandar Markovic
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Aleksandar Markovic @ 2018-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, jancraig, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment that contains a basic description of MXU ASE.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..23e21c5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1389,6 +1389,26 @@ enum {
OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
+
+/*
+ * AN OVERVIEW OF MXU EXTENSTION INSTRUCTION SET
+ * =============================================
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing applications. MXU instruction set is used in Xburst family
+ * of microprocessors by Ingenic.
+ *
+ * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
+ * the control register.
+ *
+ * Compiled after:
+ *
+ * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
+ * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
+ */
+
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for MXU ASE
2018-10-16 12:14 [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE Aleksandar Markovic
@ 2018-10-16 12:14 ` Aleksandar Markovic
2018-10-16 13:33 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of " Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values " Aleksandar Markovic
3 siblings, 1 reply; 9+ messages in thread
From: Aleksandar Markovic @ 2018-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, jancraig, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 23e21c5..73d971e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1402,6 +1402,94 @@ enum {
* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
* the control register.
*
+ * The notation used in MXU assembler mnemonics:
+ *
+ * XRa, XRb, XRa, XRb - MXU registers
+ * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
+ * s12 - a subfield of an instruction code
+ * strd2 - a subfield of an instruction code
+ * eptn2 - a subfield of an instruction code
+ * eptn3 - a subfield of an instruction code
+ * optn2 - a subfield of an instruction code
+ * optn3 - a subfield of an instruction code
+ * sft4 - a subfield of an instruction code
+ *
+ * Load/Store instructions Multiplication instructions
+ * ----------------------- ---------------------------
+ *
+ * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
+ * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
+ * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt
+ * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt
+ * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
+ * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
+ * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2
+ * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2
+ * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2
+ * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
+ * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd
+ * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd
+ * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2
+ * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2
+ * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2
+ * S16SDI XRa, Rb, s10, eptn2
+ * S8LDD XRa, Rb, s8, eptn3
+ * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions
+ * S8LDI XRa, Rb, s8, eptn3 -------------------------------------
+ * S8SDI XRa, Rb, s8, eptn3
+ * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2
+ * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd
+ * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2
+ * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2
+ * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2
+ * S32CPS XRa, XRb, XRc
+ * Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
+ * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2
+ * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2
+ * D16ASUM XRa, XRb, XRc, XRd, eptn2
+ * S32MAX XRa, XRb, XRc D16CPS XRa, XRb,
+ * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc
+ * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc
+ * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2
+ * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2
+ * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2
+ * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc
+ * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd
+ * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc
+ * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc
+ * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd
+ * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd
+ * Q8SLT XRa, XRb, XRc
+ * Q8SLTU XRa, XRb, XRc
+ * Q8MOVZ XRa, XRb, XRc Shift instructions
+ * Q8MOVN XRa, XRb, XRc ------------------
+ *
+ * D32SLL XRa, XRb, XRc, XRd, sft4
+ * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4
+ * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4
+ * D32SARL XRa, XRb, XRc, sft4
+ * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb
+ * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb
+ * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb
+ * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb
+ * Q16SLL XRa, XRb, XRc, XRd, sft4
+ * Q16SLR XRa, XRb, XRc, XRd, sft4
+ * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
+ * ------------------------- Q16SLLV XRa, XRb, Rb
+ * Q16SLRV XRa, XRb, Rb
+ * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
+ * S32ALN XRa, XRb, XRc, Rb
+ * S32ALNI XRa, XRb, XRc, s3
+ * S32LUI XRa, s8, optn3 Move instructions
+ * S32EXTR XRa, XRb, Rb, bits5 -----------------
+ * S32EXTRV XRa, XRb, Rs, Rt
+ * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
+ * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
+ *
* Compiled after:
*
* "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of MXU ASE
2018-10-16 12:14 [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for " Aleksandar Markovic
@ 2018-10-16 12:14 ` Aleksandar Markovic
2018-10-16 13:34 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values " Aleksandar Markovic
3 siblings, 1 reply; 9+ messages in thread
From: Aleksandar Markovic @ 2018-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, jancraig, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment that contains an organizational chart of MXU ASE
instructions.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 73d971e..4dfc360 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1490,6 +1490,162 @@ enum {
* Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
* Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
*
+ *
+ * bits
+ * 05..00
+ *
+ * ┌─ 000000 ─ OPC_MXU_S32MADD
+ * ├─ 000001 ─ OPC_MXU_S32MADDU
+ * ├─ 000010 ─ <not assigned>
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
+ * │ ├─ 001 ─ OPC_MXU_S32MIN
+ * │ ├─ 010 ─ OPC_MXU_D16MAX
+ * │ ├─ 011 ─ OPC_MXU_D16MIN
+ * │ ├─ 100 ─ OPC_MXU_Q8MAX
+ * │ ├─ 101 ─ OPC_MXU_Q8MIN
+ * │ ├─ 110 ─ OPC_MXU_Q8SLT
+ * │ └─ 111 ─ OPC_MXU_Q8SLTU
+ * ├─ 000100 ─ OPC_MXU_S32MSUB
+ * ├─ 000101 ─ OPC_MXU_S32MSUBU 20..18 (25..21 must be 0,
+ * │ except for Q8ADD)
+ * ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
+ * │ ├─ 001 ─ OPC_MXU_D16SLT
+ * │ ├─ 010 ─ OPC_MXU_D16AVG
+ * │ ├─ 011 ─ OPC_MXU_D16AVGR
+ * │ ├─ 100 ─ OPC_MXU_Q8AVG
+ * │ ├─ 101 ─ OPC_MXU_Q8AVGR
+ * │ └─ 111 ─ OPC_MXU_Q8ADD
+ * │
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
+ * │ ├─ 010 ─ OPC_MXU_D16CPS
+ * │ ├─ 100 ─ OPC_MXU_Q8ABD
+ * │ └─ 110 ─ OPC_MXU_Q16SAT
+ * ├─ 001000 ─ OPC_MXU_D16MUL
+ * │ 25..24
+ * ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
+ * │ └─ 01 ─ OPC_MXU_D16MULE
+ * ├─ 001010 ─ OPC_MXU_D16MAC
+ * ├─ 001011 ─ OPC_MXU_D16MACF
+ * ├─ 001100 ─ OPC_MXU_D16MADL
+ * │ 25..24
+ * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD
+ * │ └─ 01 ─ OPC_MXU_S16MAD_1
+ * ├─ 001110 ─ OPC_MXU_Q16ADD
+ * ├─ 001111 ─ OPC_MXU_D16MACE
+ * │ 23
+ * ├─ 010000 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD
+ * │ └─ 1 ─ OPC_MXU_S32LDDR
+ * │
+ * │ 23
+ * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD
+ * │ └─ 1 ─ OPC_MXU_S32STDR
+ * │
+ * │ 13..10
+ * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32LDDV
+ * │ └─ 0001 ─ OPC_MXU_S32LDDVR
+ * │
+ * │ 13..10
+ * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ 0000 ─ OPC_MXU_S32TDV
+ * │ └─ 0001 ─ OPC_MXU_S32TDVR
+ * │
+ * │ 23
+ * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI
+ * │ └─ 1 ─ OPC_MXU_S32LDIR
+ * │
+ * │ 23
+ * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI
+ * │ └─ 1 ─ OPC_MXU_S32SDIR
+ * │
+ * │ 13..10
+ * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32LDIV
+ * │ └─ 0001 ─ OPC_MXU_S32LDIVR
+ * │
+ * │ 13..10
+ * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ 0000 ─ OPC_MXU_S32SDIV
+ * │ └─ 0001 ─ OPC_MXU_S32SDIVR
+ * ├─ 011000 ─ OPC_MXU_D32ADD
+ * │
+ * MXU ├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC
+ * opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM
+ * │ └─ 10 ─ OPC_MXU_D32ASUM
+ * ├─ 011010 ─ <not assigned>
+ * │
+ * ├─ 011011 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q16ACC
+ * │ ├─ 01 ─ OPC_MXU_Q16ACCM
+ * │ └─ 10 ─ OPC_MXU_Q16ASUM
+ * │
+ * │
+ * ├─ 011100 ─ OPC_MXU__POOL15 ─┬─ 00 ─ OPC_MXU_Q8ADDE
+ * │ ├─ 01 ─ OPC_MXU_D8SUM
+ * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC
+ * ├─ 011110 ─ <not assigned>
+ * ├─ 011111 ─ <not assigned>
+ * ├─ 100000 ─ <not assigned>
+ * ├─ 100001 ─ <not assigned>
+ * ├─ 100010 ─ OPC_MXU_S8LDD
+ * ├─ 100011 ─ OPC_MXU_S8STD
+ * ├─ 100100 ─ OPC_MXU_S8LDI
+ * ├─ 100101 ─ OPC_MXU_S8SDI
+ * │
+ * ├─ 100110 ─ OPC_MXU__POOL16 ─┬─ 00 ─ OPC_MXU_S32MUL
+ * │ ├─ 00 ─ OPC_MXU_S32MULU
+ * │ ├─ 00 ─ OPC_MXU_S32EXTR
+ * │ └─ 00 ─ OPC_MXU_S32EXTRV
+ * │
+ * │
+ * ├─ 100111 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_D32SARW
+ * │ ├─ 001 ─ OPC_MXU_S32ALN
+ * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
+ * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR
+ * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
+ * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
+ * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
+ * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
+ * ├─ 101000 ─ <not assigned>
+ * ├─ 101001 ─ <not assigned>
+ * ├─ 101010 ─ <not assigned>
+ * ├─ 101011 ─ <not assigned>
+ * ├─ 101100 ─ <not assigned>
+ * ├─ 101101 ─ <not assigned>
+ * ├─ 101110 ─ OPC_MXU_S32M2I
+ * ├─ 101111 ─ OPC_MXU_S32I2M
+ * ├─ 110000 ─ OPC_MXU_D32SLL
+ * ├─ 110001 ─ OPC_MXU_D32SLR
+ * ├─ 110010 ─ OPC_MXU_D32SARL
+ * ├─ 110011 ─ OPC_MXU_D32SAR
+ * ├─ 110100 ─ OPC_MXU_Q16SLL
+ * ├─ 110101 ─ OPC_MXU_Q16SLR
+ * ├─ 110110 ─ OPC_MXU__POOL18 ─┬─ 000 ─ OPC_MXU_D32SLLV
+ * │ ├─ 001 ─ OPC_MXU_D32SLRV
+ * │ ├─ 010 ─ OPC_MXU_D32SARV
+ * │ ├─ 011 ─ OPC_MXU_Q16SLLV
+ * │ ├─ 100 ─ OPC_MXU_Q16SLRV
+ * │ └─ 101 ─ OPC_MXU_Q16SARV
+ * ├─ 110111 ─ OPC_MXU_Q16SAR
+ * │
+ * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
+ * │ └─ 01 ─ OPC_MXU_Q8MULSU
+ * │
+ * │
+ * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
+ * │ ├─ 001 ─ OPC_MXU_Q8MOVN
+ * │ ├─ 010 ─ OPC_MXU_D16MOVZ
+ * │ ├─ 011 ─ OPC_MXU_D16MOVN
+ * │ ├─ 100 ─ OPC_MXU_S32MOVZ
+ * │ └─ 101 ─ OPC_MXU_S32MOV
+ * │
+ * │
+ * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
+ * │ └─ 10 ─ OPC_MXU_Q8MACSU
+ * ├─ 111011 ─ OPC_MXU_Q16SCOP
+ * ├─ 111100 ─ OPC_MXU_Q8MADL
+ * ├─ 111101 ─ OPC_MXU_S32SFL
+ * ├─ 111110 ─ OPC_MXU_Q8SAD
+ * └─ 111111 ─ <not assigned>
+ *
+ *
* Compiled after:
*
* "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values of MXU ASE
2018-10-16 12:14 [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes Aleksandar Markovic
` (2 preceding siblings ...)
2018-10-16 12:14 ` [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of " Aleksandar Markovic
@ 2018-10-16 12:14 ` Aleksandar Markovic
2018-10-16 13:40 ` Stefan Markovic
3 siblings, 1 reply; 9+ messages in thread
From: Aleksandar Markovic @ 2018-10-16 12:14 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, jancraig, amarkovic, smarkovic, pjovanovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add opcode values for all instructions in MXU ASE.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 276 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 276 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4dfc360..941b546 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1652,6 +1652,282 @@ enum {
* Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
*/
+enum {
+ OPC_MXU_S32MADD = 0x00,
+ OPC_MXU_S32MADDU = 0x01,
+ /* not assigned 0x02 */
+ OPC_MXU__POOL00 = 0x03,
+ OPC_MXU_S32MSUB = 0x04,
+ OPC_MXU_S32MSUBU = 0x05,
+ OPC_MXU__POOL01 = 0x06,
+ OPC_MXU__POOL02 = 0x07,
+ OPC_MXU_D16MUL = 0x08,
+ OPC_MXU__POOL03 = 0x09,
+ OPC_MXU_D16MAC = 0x0A,
+ OPC_MXU_D16MACF = 0x0B,
+ OPC_MXU_D16MADL = 0x0C,
+ OPC_MXU__POOL04 = 0x0D,
+ OPC_MXU_Q16ADD = 0x0E,
+ OPC_MXU_D16MACE = 0x0F,
+ OPC_MXU__POOL05 = 0x10,
+ OPC_MXU__POOL06 = 0x11,
+ OPC_MXU__POOL07 = 0x12,
+ OPC_MXU__POOL08 = 0x13,
+ OPC_MXU__POOL09 = 0x14,
+ OPC_MXU__POOL10 = 0x15,
+ OPC_MXU__POOL11 = 0x16,
+ OPC_MXU__POOL12 = 0x17,
+ OPC_MXU_D32ADD = 0x18,
+ OPC_MXU__POOL13 = 0x19,
+ /* not assigned 0x1A */
+ OPC_MXU__POOL14 = 0x1B,
+ OPC_MXU__POOL15 = 0x1C,
+ OPC_MXU_Q8ACCE = 0x1D,
+ /* not assigned 0x1E */
+ /* not assigned 0x1F */
+ /* not assigned 0x20 */
+ /* not assigned 0x21 */
+ OPC_MXU_S8LDD = 0x22,
+ OPC_MXU_S8STD = 0x23,
+ OPC_MXU_S8LDI = 0x24,
+ OPC_MXU_S8SDI = 0x25,
+ OPC_MXU__POOL16 = 0x26,
+ OPC_MXU__POOL17 = 0x27,
+ OPC_MXU_LXB = 0x28,
+ /* not assigned 0x29 */
+ OPC_MXU_S16LDD = 0x2A,
+ OPC_MXU_S16STD = 0x2B,
+ OPC_MXU_S16LDI = 0x2C,
+ OPC_MXU_S16SDI = 0x2D,
+ OPC_MXU_S32M2I = 0x2E,
+ OPC_MXU_S32I2M = 0x2F,
+ OPC_MXU_D32SLL = 0x30,
+ OPC_MXU_D32SLR = 0x31,
+ OPC_MXU_D32SARL = 0x32,
+ OPC_MXU_D32SAR = 0x33,
+ OPC_MXU_Q16SLL = 0x34,
+ OPC_MXU_Q16SLR = 0x35,
+ OPC_MXU__POOL18 = 0x36,
+ OPC_MXU_Q16SAR = 0x37,
+ OPC_MXU__POOL19 = 0x38,
+ OPC_MXU__POOL20 = 0x39,
+ OPC_MXU__POOL21 = 0x3A,
+ OPC_MXU_Q16SCOP = 0x3B,
+ OPC_MXU_Q8MADL = 0x3C,
+ OPC_MXU_S32SFL = 0x3D,
+ OPC_MXU_Q8SAD = 0x3E,
+ /* not assigned 0x3F */
+};
+
+
+/*
+ * MXU pool 00
+ */
+enum {
+ OPC_MXU_S32MAX = 0x00,
+ OPC_MXU_S32MIN = 0x01,
+ OPC_MXU_D16MAX = 0x02,
+ OPC_MXU_D16MIN = 0x03,
+ OPC_MXU_Q8MAX = 0x04,
+ OPC_MXU_Q8MIN = 0x05,
+ OPC_MXU_Q8SLT = 0x06,
+ OPC_MXU_Q8SLTU = 0x07,
+};
+
+/*
+ * MXU pool 01
+ */
+enum {
+ OPC_MXU_S32SLT = 0x00,
+ OPC_MXU_D16SLT = 0x01,
+ OPC_MXU_D16AVG = 0x02,
+ OPC_MXU_D16AVGR = 0x03,
+ OPC_MXU_Q8AVG = 0x04,
+ OPC_MXU_Q8AVGR = 0x05,
+ OPC_MXU_Q8ADD = 0x07,
+};
+
+/*
+ * MXU pool 02
+ */
+enum {
+ OPC_MXU_S32CPS = 0x00,
+ OPC_MXU_D16CPS = 0x02,
+ OPC_MXU_Q8ABD = 0x04,
+ OPC_MXU_Q16SAT = 0x06,
+};
+
+/*
+ * MXU pool 03
+ */
+enum {
+ OPC_MXU_D16MULF = 0x00,
+ OPC_MXU_D16MULE = 0x01,
+};
+
+/*
+ * MXU pool 04
+ */
+enum {
+ OPC_MXU_S16MAD = 0x00,
+ OPC_MXU_S16MAD_1 = 0x01,
+};
+
+/*
+ * MXU pool 05
+ */
+enum {
+ OPC_MXU_S32LDD = 0x00,
+ OPC_MXU_S32LDDR = 0x01,
+};
+
+/*
+ * MXU pool 06
+ */
+enum {
+ OPC_MXU_S32STD = 0x00,
+ OPC_MXU_S32STDR = 0x01,
+};
+
+/*
+ * MXU pool 07
+ */
+enum {
+ OPC_MXU_S32LDDV = 0x00,
+ OPC_MXU_S32LDDVR = 0x01,
+};
+
+/*
+ * MXU pool 08
+ */
+enum {
+ OPC_MXU_S32TDV = 0x00,
+ OPC_MXU_S32TDVR = 0x01,
+};
+
+/*
+ * MXU pool 09
+ */
+enum {
+ OPC_MXU_S32LDI = 0x00,
+ OPC_MXU_S32LDIR = 0x01,
+};
+
+/*
+ * MXU pool 10
+ */
+enum {
+ OPC_MXU_S32SDI = 0x00,
+ OPC_MXU_S32SDIR = 0x01,
+};
+
+/*
+ * MXU pool 11
+ */
+enum {
+ OPC_MXU_S32LDIV = 0x00,
+ OPC_MXU_S32LDIVR = 0x01,
+};
+
+/*
+ * MXU pool 12
+ */
+enum {
+ OPC_MXU_S32SDIV = 0x00,
+ OPC_MXU_S32SDIVR = 0x01,
+};
+
+/*
+ * MXU pool 13
+ */
+enum {
+ OPC_MXU_D32ACC = 0x00,
+ OPC_MXU_D32ACCM = 0x01,
+ OPC_MXU_D32ASUM = 0x02,
+};
+
+/*
+ * MXU pool 14
+ */
+enum {
+ OPC_MXU_Q16ACC = 0x00,
+ OPC_MXU_Q16ACCM = 0x01,
+ OPC_MXU_Q16ASUM = 0x02,
+};
+
+/*
+ * MXU pool 15
+ */
+enum {
+ OPC_MXU_Q8ADDE = 0x00,
+ OPC_MXU_D8SUM = 0x01,
+ OPC_MXU_D8SUMC = 0x02,
+};
+
+/*
+ * MXU pool 16
+ */
+enum {
+ OPC_MXU_S32MUL = 0x00,
+ OPC_MXU_S32MULU = 0x01,
+ OPC_MXU_S32EXTR = 0x02,
+ OPC_MXU_S32EXTRV = 0x03,
+};
+
+/*
+ * MXU pool 17
+ */
+enum {
+ OPC_MXU_D32SARW = 0x00,
+ OPC_MXU_S32ALN = 0x01,
+ OPC_MXU_S32ALNI = 0x02,
+ OPC_MXU_S32NOR = 0x03,
+ OPC_MXU_S32AND = 0x04,
+ OPC_MXU_S32OR = 0x05,
+ OPC_MXU_S32XOR = 0x06,
+ OPC_MXU_S32LUI = 0x07,
+};
+
+/*
+ * MXU pool 18
+ */
+enum {
+ OPC_MXU_D32SLLV = 0x00,
+ OPC_MXU_D32SLRV = 0x01,
+ OPC_MXU_D32SARV = 0x03,
+ OPC_MXU_Q16SLLV = 0x04,
+ OPC_MXU_Q16SLRV = 0x05,
+ OPC_MXU_Q16SARV = 0x07,
+};
+
+/*
+ * MXU pool 19
+ */
+enum {
+ OPC_MXU_Q8MUL = 0x00,
+ OPC_MXU_Q8MULSU = 0x01,
+};
+
+/*
+ * MXU pool 20
+ */
+enum {
+ OPC_MXU_Q8MOVZ = 0x00,
+ OPC_MXU_Q8MOVN = 0x01,
+ OPC_MXU_D16MOVZ = 0x02,
+ OPC_MXU_D16MOVN = 0x03,
+ OPC_MXU_S32MOVZ = 0x04,
+ OPC_MXU_S32MOVN = 0x05,
+};
+
+/*
+ * MXU pool 21
+ */
+enum {
+ OPC_MXU_Q8MAC = 0x00,
+ OPC_MXU_Q8MACSU = 0x01,
+};
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE
2018-10-16 12:14 ` [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE Aleksandar Markovic
@ 2018-10-16 13:27 ` Stefan Markovic
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Markovic @ 2018-10-16 13:27 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, jancraig, amarkovic, pjovanovic
On 16.10.18. 14:14, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add a comment that contains a basic description of MXU ASE.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index ab16cdb..23e21c5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1389,6 +1389,26 @@ enum {
> OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
> };
>
> +
> +/*
> + * AN OVERVIEW OF MXU EXTENSTION INSTRUCTION SET
> + * =============================================
Misspelled EXTENSION. Otherwise:
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> + *
> + * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
> + * instructions set. It is designed to fit the needs of signal, graphical and
> + * video processing applications. MXU instruction set is used in Xburst family
> + * of microprocessors by Ingenic.
> + *
> + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
> + * the control register.
> + *
> + * Compiled after:
> + *
> + * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
> + * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
> + */
> +
> +
> /* global register indices */
> static TCGv cpu_gpr[32], cpu_PC;
> static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for MXU ASE
2018-10-16 12:14 ` [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for " Aleksandar Markovic
@ 2018-10-16 13:33 ` Stefan Markovic
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Markovic @ 2018-10-16 13:33 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, jancraig, amarkovic, pjovanovic
On 16.10.18. 14:14, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add a comment that contains a list all MXU instructions,
> expressed in assembler mnemonics.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 23e21c5..73d971e 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1402,6 +1402,94 @@ enum {
> * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
> * the control register.
> *
> + * The notation used in MXU assembler mnemonics:
> + *
> + * XRa, XRb, XRa, XRb - MXU registers
XRa and XRb duplicated. Did You mean XRc and XRd instead? Otherwise:
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> + * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
> + * s12 - a subfield of an instruction code
> + * strd2 - a subfield of an instruction code
> + * eptn2 - a subfield of an instruction code
> + * eptn3 - a subfield of an instruction code
> + * optn2 - a subfield of an instruction code
> + * optn3 - a subfield of an instruction code
> + * sft4 - a subfield of an instruction code
> + *
> + * Load/Store instructions Multiplication instructions
> + * ----------------------- ---------------------------
> + *
> + * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
> + * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
> + * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt
> + * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt
> + * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
> + * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
> + * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2
> + * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2
> + * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2
> + * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
> + * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
> + * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
> + * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
> + * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
> + * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd
> + * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd
> + * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2
> + * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2
> + * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2
> + * S16SDI XRa, Rb, s10, eptn2
> + * S8LDD XRa, Rb, s8, eptn3
> + * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions
> + * S8LDI XRa, Rb, s8, eptn3 -------------------------------------
> + * S8SDI XRa, Rb, s8, eptn3
> + * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2
> + * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd
> + * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2
> + * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2
> + * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2
> + * S32CPS XRa, XRb, XRc
> + * Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
> + * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2
> + * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2
> + * D16ASUM XRa, XRb, XRc, XRd, eptn2
> + * S32MAX XRa, XRb, XRc D16CPS XRa, XRb,
> + * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc
> + * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc
> + * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2
> + * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2
> + * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2
> + * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc
> + * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd
> + * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc
> + * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc
> + * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd
> + * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd
> + * Q8SLT XRa, XRb, XRc
> + * Q8SLTU XRa, XRb, XRc
> + * Q8MOVZ XRa, XRb, XRc Shift instructions
> + * Q8MOVN XRa, XRb, XRc ------------------
> + *
> + * D32SLL XRa, XRb, XRc, XRd, sft4
> + * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4
> + * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4
> + * D32SARL XRa, XRb, XRc, sft4
> + * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb
> + * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb
> + * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb
> + * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb
> + * Q16SLL XRa, XRb, XRc, XRd, sft4
> + * Q16SLR XRa, XRb, XRc, XRd, sft4
> + * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
> + * ------------------------- Q16SLLV XRa, XRb, Rb
> + * Q16SLRV XRa, XRb, Rb
> + * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
> + * S32ALN XRa, XRb, XRc, Rb
> + * S32ALNI XRa, XRb, XRc, s3
> + * S32LUI XRa, s8, optn3 Move instructions
> + * S32EXTR XRa, XRb, Rb, bits5 -----------------
> + * S32EXTRV XRa, XRb, Rs, Rt
> + * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
> + * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
> + *
> * Compiled after:
> *
> * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of MXU ASE
2018-10-16 12:14 ` [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of " Aleksandar Markovic
@ 2018-10-16 13:34 ` Stefan Markovic
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Markovic @ 2018-10-16 13:34 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, jancraig, amarkovic, pjovanovic
On 16.10.18. 14:14, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add a comment that contains an organizational chart of MXU ASE
> instructions.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 156 insertions(+)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 73d971e..4dfc360 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1490,6 +1490,162 @@ enum {
> * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
> * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
> *
> + *
> + * bits
> + * 05..00
> + *
> + * ┌─ 000000 ─ OPC_MXU_S32MADD
> + * ├─ 000001 ─ OPC_MXU_S32MADDU
> + * ├─ 000010 ─ <not assigned>
> + * │ 20..18 (25..21 must be 0)
> + * ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
> + * │ ├─ 001 ─ OPC_MXU_S32MIN
> + * │ ├─ 010 ─ OPC_MXU_D16MAX
> + * │ ├─ 011 ─ OPC_MXU_D16MIN
> + * │ ├─ 100 ─ OPC_MXU_Q8MAX
> + * │ ├─ 101 ─ OPC_MXU_Q8MIN
> + * │ ├─ 110 ─ OPC_MXU_Q8SLT
> + * │ └─ 111 ─ OPC_MXU_Q8SLTU
> + * ├─ 000100 ─ OPC_MXU_S32MSUB
> + * ├─ 000101 ─ OPC_MXU_S32MSUBU 20..18 (25..21 must be 0,
> + * │ except for Q8ADD)
> + * ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
> + * │ ├─ 001 ─ OPC_MXU_D16SLT
> + * │ ├─ 010 ─ OPC_MXU_D16AVG
> + * │ ├─ 011 ─ OPC_MXU_D16AVGR
> + * │ ├─ 100 ─ OPC_MXU_Q8AVG
> + * │ ├─ 101 ─ OPC_MXU_Q8AVGR
> + * │ └─ 111 ─ OPC_MXU_Q8ADD
> + * │
> + * │ 20..18 (25..21 must be 0)
> + * ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
> + * │ ├─ 010 ─ OPC_MXU_D16CPS
> + * │ ├─ 100 ─ OPC_MXU_Q8ABD
> + * │ └─ 110 ─ OPC_MXU_Q16SAT
> + * ├─ 001000 ─ OPC_MXU_D16MUL
> + * │ 25..24
> + * ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
> + * │ └─ 01 ─ OPC_MXU_D16MULE
> + * ├─ 001010 ─ OPC_MXU_D16MAC
> + * ├─ 001011 ─ OPC_MXU_D16MACF
> + * ├─ 001100 ─ OPC_MXU_D16MADL
> + * │ 25..24
> + * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD
> + * │ └─ 01 ─ OPC_MXU_S16MAD_1
> + * ├─ 001110 ─ OPC_MXU_Q16ADD
> + * ├─ 001111 ─ OPC_MXU_D16MACE
> + * │ 23
> + * ├─ 010000 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD
> + * │ └─ 1 ─ OPC_MXU_S32LDDR
> + * │
> + * │ 23
> + * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD
> + * │ └─ 1 ─ OPC_MXU_S32STDR
> + * │
> + * │ 13..10
> + * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32LDDV
> + * │ └─ 0001 ─ OPC_MXU_S32LDDVR
> + * │
> + * │ 13..10
> + * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ 0000 ─ OPC_MXU_S32TDV
> + * │ └─ 0001 ─ OPC_MXU_S32TDVR
> + * │
> + * │ 23
> + * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI
> + * │ └─ 1 ─ OPC_MXU_S32LDIR
> + * │
> + * │ 23
> + * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI
> + * │ └─ 1 ─ OPC_MXU_S32SDIR
> + * │
> + * │ 13..10
> + * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32LDIV
> + * │ └─ 0001 ─ OPC_MXU_S32LDIVR
> + * │
> + * │ 13..10
> + * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ 0000 ─ OPC_MXU_S32SDIV
> + * │ └─ 0001 ─ OPC_MXU_S32SDIVR
> + * ├─ 011000 ─ OPC_MXU_D32ADD
> + * │
> + * MXU ├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC
> + * opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM
> + * │ └─ 10 ─ OPC_MXU_D32ASUM
> + * ├─ 011010 ─ <not assigned>
> + * │
> + * ├─ 011011 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q16ACC
> + * │ ├─ 01 ─ OPC_MXU_Q16ACCM
> + * │ └─ 10 ─ OPC_MXU_Q16ASUM
> + * │
> + * │
> + * ├─ 011100 ─ OPC_MXU__POOL15 ─┬─ 00 ─ OPC_MXU_Q8ADDE
> + * │ ├─ 01 ─ OPC_MXU_D8SUM
> + * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC
> + * ├─ 011110 ─ <not assigned>
> + * ├─ 011111 ─ <not assigned>
> + * ├─ 100000 ─ <not assigned>
> + * ├─ 100001 ─ <not assigned>
> + * ├─ 100010 ─ OPC_MXU_S8LDD
> + * ├─ 100011 ─ OPC_MXU_S8STD
> + * ├─ 100100 ─ OPC_MXU_S8LDI
> + * ├─ 100101 ─ OPC_MXU_S8SDI
> + * │
> + * ├─ 100110 ─ OPC_MXU__POOL16 ─┬─ 00 ─ OPC_MXU_S32MUL
> + * │ ├─ 00 ─ OPC_MXU_S32MULU
> + * │ ├─ 00 ─ OPC_MXU_S32EXTR
> + * │ └─ 00 ─ OPC_MXU_S32EXTRV
> + * │
> + * │
> + * ├─ 100111 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_D32SARW
> + * │ ├─ 001 ─ OPC_MXU_S32ALN
> + * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
> + * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR
> + * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
> + * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
> + * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
> + * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
> + * ├─ 101000 ─ <not assigned>
> + * ├─ 101001 ─ <not assigned>
> + * ├─ 101010 ─ <not assigned>
> + * ├─ 101011 ─ <not assigned>
> + * ├─ 101100 ─ <not assigned>
> + * ├─ 101101 ─ <not assigned>
> + * ├─ 101110 ─ OPC_MXU_S32M2I
> + * ├─ 101111 ─ OPC_MXU_S32I2M
> + * ├─ 110000 ─ OPC_MXU_D32SLL
> + * ├─ 110001 ─ OPC_MXU_D32SLR
> + * ├─ 110010 ─ OPC_MXU_D32SARL
> + * ├─ 110011 ─ OPC_MXU_D32SAR
> + * ├─ 110100 ─ OPC_MXU_Q16SLL
> + * ├─ 110101 ─ OPC_MXU_Q16SLR
> + * ├─ 110110 ─ OPC_MXU__POOL18 ─┬─ 000 ─ OPC_MXU_D32SLLV
> + * │ ├─ 001 ─ OPC_MXU_D32SLRV
> + * │ ├─ 010 ─ OPC_MXU_D32SARV
> + * │ ├─ 011 ─ OPC_MXU_Q16SLLV
> + * │ ├─ 100 ─ OPC_MXU_Q16SLRV
> + * │ └─ 101 ─ OPC_MXU_Q16SARV
> + * ├─ 110111 ─ OPC_MXU_Q16SAR
> + * │
> + * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
> + * │ └─ 01 ─ OPC_MXU_Q8MULSU
> + * │
> + * │
> + * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
> + * │ ├─ 001 ─ OPC_MXU_Q8MOVN
> + * │ ├─ 010 ─ OPC_MXU_D16MOVZ
> + * │ ├─ 011 ─ OPC_MXU_D16MOVN
> + * │ ├─ 100 ─ OPC_MXU_S32MOVZ
> + * │ └─ 101 ─ OPC_MXU_S32MOV
> + * │
> + * │
> + * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
> + * │ └─ 10 ─ OPC_MXU_Q8MACSU
> + * ├─ 111011 ─ OPC_MXU_Q16SCOP
> + * ├─ 111100 ─ OPC_MXU_Q8MADL
> + * ├─ 111101 ─ OPC_MXU_S32SFL
> + * ├─ 111110 ─ OPC_MXU_Q8SAD
> + * └─ 111111 ─ <not assigned>
> + *
> + *
> * Compiled after:
> *
> * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values of MXU ASE
2018-10-16 12:14 ` [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values " Aleksandar Markovic
@ 2018-10-16 13:40 ` Stefan Markovic
0 siblings, 0 replies; 9+ messages in thread
From: Stefan Markovic @ 2018-10-16 13:40 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: aurelien, jancraig, amarkovic, pjovanovic
On 16.10.18. 14:14, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Add opcode values for all instructions in MXU ASE.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 276 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 276 insertions(+)
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 4dfc360..941b546 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1652,6 +1652,282 @@ enum {
> * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
> */
>
> +enum {
> + OPC_MXU_S32MADD = 0x00,
> + OPC_MXU_S32MADDU = 0x01,
> + /* not assigned 0x02 */
> + OPC_MXU__POOL00 = 0x03,
> + OPC_MXU_S32MSUB = 0x04,
> + OPC_MXU_S32MSUBU = 0x05,
> + OPC_MXU__POOL01 = 0x06,
> + OPC_MXU__POOL02 = 0x07,
> + OPC_MXU_D16MUL = 0x08,
> + OPC_MXU__POOL03 = 0x09,
> + OPC_MXU_D16MAC = 0x0A,
> + OPC_MXU_D16MACF = 0x0B,
> + OPC_MXU_D16MADL = 0x0C,
> + OPC_MXU__POOL04 = 0x0D,
> + OPC_MXU_Q16ADD = 0x0E,
> + OPC_MXU_D16MACE = 0x0F,
> + OPC_MXU__POOL05 = 0x10,
> + OPC_MXU__POOL06 = 0x11,
> + OPC_MXU__POOL07 = 0x12,
> + OPC_MXU__POOL08 = 0x13,
> + OPC_MXU__POOL09 = 0x14,
> + OPC_MXU__POOL10 = 0x15,
> + OPC_MXU__POOL11 = 0x16,
> + OPC_MXU__POOL12 = 0x17,
> + OPC_MXU_D32ADD = 0x18,
> + OPC_MXU__POOL13 = 0x19,
> + /* not assigned 0x1A */
> + OPC_MXU__POOL14 = 0x1B,
> + OPC_MXU__POOL15 = 0x1C,
> + OPC_MXU_Q8ACCE = 0x1D,
> + /* not assigned 0x1E */
> + /* not assigned 0x1F */
> + /* not assigned 0x20 */
> + /* not assigned 0x21 */
> + OPC_MXU_S8LDD = 0x22,
> + OPC_MXU_S8STD = 0x23,
> + OPC_MXU_S8LDI = 0x24,
> + OPC_MXU_S8SDI = 0x25,
> + OPC_MXU__POOL16 = 0x26,
> + OPC_MXU__POOL17 = 0x27,
> + OPC_MXU_LXB = 0x28,
> + /* not assigned 0x29 */
> + OPC_MXU_S16LDD = 0x2A,
> + OPC_MXU_S16STD = 0x2B,
> + OPC_MXU_S16LDI = 0x2C,
> + OPC_MXU_S16SDI = 0x2D,
> + OPC_MXU_S32M2I = 0x2E,
> + OPC_MXU_S32I2M = 0x2F,
> + OPC_MXU_D32SLL = 0x30,
> + OPC_MXU_D32SLR = 0x31,
> + OPC_MXU_D32SARL = 0x32,
> + OPC_MXU_D32SAR = 0x33,
> + OPC_MXU_Q16SLL = 0x34,
> + OPC_MXU_Q16SLR = 0x35,
> + OPC_MXU__POOL18 = 0x36,
> + OPC_MXU_Q16SAR = 0x37,
> + OPC_MXU__POOL19 = 0x38,
> + OPC_MXU__POOL20 = 0x39,
> + OPC_MXU__POOL21 = 0x3A,
> + OPC_MXU_Q16SCOP = 0x3B,
> + OPC_MXU_Q8MADL = 0x3C,
> + OPC_MXU_S32SFL = 0x3D,
> + OPC_MXU_Q8SAD = 0x3E,
> + /* not assigned 0x3F */
> +};
> +
> +
> +/*
> + * MXU pool 00
> + */
> +enum {
> + OPC_MXU_S32MAX = 0x00,
> + OPC_MXU_S32MIN = 0x01,
> + OPC_MXU_D16MAX = 0x02,
> + OPC_MXU_D16MIN = 0x03,
> + OPC_MXU_Q8MAX = 0x04,
> + OPC_MXU_Q8MIN = 0x05,
> + OPC_MXU_Q8SLT = 0x06,
> + OPC_MXU_Q8SLTU = 0x07,
> +};
> +
> +/*
> + * MXU pool 01
> + */
> +enum {
> + OPC_MXU_S32SLT = 0x00,
> + OPC_MXU_D16SLT = 0x01,
> + OPC_MXU_D16AVG = 0x02,
> + OPC_MXU_D16AVGR = 0x03,
> + OPC_MXU_Q8AVG = 0x04,
> + OPC_MXU_Q8AVGR = 0x05,
> + OPC_MXU_Q8ADD = 0x07,
> +};
> +
> +/*
> + * MXU pool 02
> + */
> +enum {
> + OPC_MXU_S32CPS = 0x00,
> + OPC_MXU_D16CPS = 0x02,
> + OPC_MXU_Q8ABD = 0x04,
> + OPC_MXU_Q16SAT = 0x06,
> +};
> +
> +/*
> + * MXU pool 03
> + */
> +enum {
> + OPC_MXU_D16MULF = 0x00,
> + OPC_MXU_D16MULE = 0x01,
> +};
> +
> +/*
> + * MXU pool 04
> + */
> +enum {
> + OPC_MXU_S16MAD = 0x00,
> + OPC_MXU_S16MAD_1 = 0x01,
> +};
> +
> +/*
> + * MXU pool 05
> + */
> +enum {
> + OPC_MXU_S32LDD = 0x00,
> + OPC_MXU_S32LDDR = 0x01,
> +};
> +
> +/*
> + * MXU pool 06
> + */
> +enum {
> + OPC_MXU_S32STD = 0x00,
> + OPC_MXU_S32STDR = 0x01,
> +};
> +
> +/*
> + * MXU pool 07
> + */
> +enum {
> + OPC_MXU_S32LDDV = 0x00,
> + OPC_MXU_S32LDDVR = 0x01,
> +};
> +
> +/*
> + * MXU pool 08
> + */
> +enum {
> + OPC_MXU_S32TDV = 0x00,
> + OPC_MXU_S32TDVR = 0x01,
> +};
> +
> +/*
> + * MXU pool 09
> + */
> +enum {
> + OPC_MXU_S32LDI = 0x00,
> + OPC_MXU_S32LDIR = 0x01,
> +};
> +
> +/*
> + * MXU pool 10
> + */
> +enum {
> + OPC_MXU_S32SDI = 0x00,
> + OPC_MXU_S32SDIR = 0x01,
> +};
> +
> +/*
> + * MXU pool 11
> + */
> +enum {
> + OPC_MXU_S32LDIV = 0x00,
> + OPC_MXU_S32LDIVR = 0x01,
> +};
> +
> +/*
> + * MXU pool 12
> + */
> +enum {
> + OPC_MXU_S32SDIV = 0x00,
> + OPC_MXU_S32SDIVR = 0x01,
> +};
> +
> +/*
> + * MXU pool 13
> + */
> +enum {
> + OPC_MXU_D32ACC = 0x00,
> + OPC_MXU_D32ACCM = 0x01,
> + OPC_MXU_D32ASUM = 0x02,
> +};
> +
> +/*
> + * MXU pool 14
> + */
> +enum {
> + OPC_MXU_Q16ACC = 0x00,
> + OPC_MXU_Q16ACCM = 0x01,
> + OPC_MXU_Q16ASUM = 0x02,
> +};
> +
> +/*
> + * MXU pool 15
> + */
> +enum {
> + OPC_MXU_Q8ADDE = 0x00,
> + OPC_MXU_D8SUM = 0x01,
> + OPC_MXU_D8SUMC = 0x02,
> +};
> +
> +/*
> + * MXU pool 16
> + */
> +enum {
> + OPC_MXU_S32MUL = 0x00,
> + OPC_MXU_S32MULU = 0x01,
> + OPC_MXU_S32EXTR = 0x02,
> + OPC_MXU_S32EXTRV = 0x03,
> +};
> +
> +/*
> + * MXU pool 17
> + */
> +enum {
> + OPC_MXU_D32SARW = 0x00,
> + OPC_MXU_S32ALN = 0x01,
> + OPC_MXU_S32ALNI = 0x02,
> + OPC_MXU_S32NOR = 0x03,
> + OPC_MXU_S32AND = 0x04,
> + OPC_MXU_S32OR = 0x05,
> + OPC_MXU_S32XOR = 0x06,
> + OPC_MXU_S32LUI = 0x07,
> +};
> +
> +/*
> + * MXU pool 18
> + */
> +enum {
> + OPC_MXU_D32SLLV = 0x00,
> + OPC_MXU_D32SLRV = 0x01,
> + OPC_MXU_D32SARV = 0x03,
> + OPC_MXU_Q16SLLV = 0x04,
> + OPC_MXU_Q16SLRV = 0x05,
> + OPC_MXU_Q16SARV = 0x07,
> +};
> +
> +/*
> + * MXU pool 19
> + */
> +enum {
> + OPC_MXU_Q8MUL = 0x00,
> + OPC_MXU_Q8MULSU = 0x01,
> +};
> +
> +/*
> + * MXU pool 20
> + */
> +enum {
> + OPC_MXU_Q8MOVZ = 0x00,
> + OPC_MXU_Q8MOVN = 0x01,
> + OPC_MXU_D16MOVZ = 0x02,
> + OPC_MXU_D16MOVN = 0x03,
> + OPC_MXU_S32MOVZ = 0x04,
> + OPC_MXU_S32MOVN = 0x05,
> +};
> +
> +/*
> + * MXU pool 21
> + */
> +enum {
> + OPC_MXU_Q8MAC = 0x00,
> + OPC_MXU_Q8MACSU = 0x01,
> +};
> +
>
> /* global register indices */
> static TCGv cpu_gpr[32], cpu_PC;
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-10-16 13:40 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-16 12:14 [Qemu-devel] [PATCH 0/4] target/mips: Add Ingenic's MXU ASE opcodes Aleksandar Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE Aleksandar Markovic
2018-10-16 13:27 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for " Aleksandar Markovic
2018-10-16 13:33 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of " Aleksandar Markovic
2018-10-16 13:34 ` Stefan Markovic
2018-10-16 12:14 ` [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values " Aleksandar Markovic
2018-10-16 13:40 ` Stefan Markovic
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