From: Julian Ganz <neither@nut.email>
To: qemu-devel@nongnu.org
Cc: Julian Ganz <neither@nut.email>,
Nicholas Piggin <npiggin@gmail.com>,
Chinmay Rath <rathc@linux.ibm.com>,
qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Subject: [PATCH v6 15/25] target/ppc: call plugin trap callbacks
Date: Thu, 4 Sep 2025 22:46:52 +0200 [thread overview]
Message-ID: <d208e845578e8573e85fb6e211f13473e95e9266.1757018626.git.neither@nut.email> (raw)
In-Reply-To: <cover.1757018626.git.neither@nut.email>
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.
This change places hooks for Power PC targets.
Signed-off-by: Julian Ganz <neither@nut.email>
---
target/ppc/excp_helper.c | 41 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 1efdc4066e..be0596e41b 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -27,6 +27,7 @@
#include "internal.h"
#include "helper_regs.h"
#include "hw/ppc/ppc.h"
+#include "qemu/plugin.h"
#include "trace.h"
@@ -404,11 +405,31 @@ static void powerpc_mcheck_checkstop(CPUPPCState *env)
powerpc_checkstop(env, "machine check with MSR[ME]=0");
}
+static void powerpc_do_plugin_vcpu_interrupt_cb(CPUState *cs, int excp,
+ uint64_t from)
+{
+ switch (excp) {
+ case POWERPC_EXCP_NONE:
+ break;
+ case POWERPC_EXCP_FIT:
+ case POWERPC_EXCP_WDT:
+ case POWERPC_EXCP_PIT:
+ case POWERPC_EXCP_SMI:
+ case POWERPC_EXCP_PERFM:
+ case POWERPC_EXCP_THERM:
+ qemu_plugin_vcpu_interrupt_cb(cs, from);
+ break;
+ default:
+ qemu_plugin_vcpu_exception_cb(cs, from);
+ }
+}
+
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
+ uint64_t last_pc = env->nip;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -456,6 +477,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
env->spr[SPR_40x_ESR] = ESR_FP;
@@ -510,12 +532,14 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->spr[srr0] = env->nip;
env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
+ uint64_t last_pc = env->nip;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -567,6 +591,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
/*
@@ -653,12 +678,14 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
env->spr[SPR_SRR0] = env->nip;
env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
+ uint64_t last_pc = env->nip;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -708,6 +735,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
/*
@@ -758,6 +786,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
if (lev == 1 && cpu->vhyp) {
cpu->vhyp_class->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_hostcall_cb(env_cpu(env), last_pc);
return;
}
@@ -803,12 +832,14 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
env->spr[SPR_SRR0] = env->nip;
env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
{
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
+ uint64_t last_pc = env->nip;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -858,6 +889,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
/*
@@ -908,6 +940,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
if (lev == 1 && cpu->vhyp) {
cpu->vhyp_class->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_hostcall_cb(env_cpu(env), last_pc);
return;
}
@@ -947,6 +980,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
env->spr[SPR_SRR0] = env->nip;
env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
@@ -954,6 +988,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0 = SPR_SRR0, srr1 = SPR_SRR1;
+ uint64_t last_pc = env->nip;
/*
* Book E does not play games with certain bits of xSRR1 being MSR save
@@ -1025,6 +1060,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
/*
@@ -1133,6 +1169,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
env->spr[srr0] = env->nip;
env->spr[srr1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
/*
@@ -1254,6 +1291,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
int srr0 = SPR_SRR0, srr1 = SPR_SRR1, lev = -1;
+ uint64_t last_pc = env->nip;
/* new srr1 value excluding must-be-zero bits */
msr = env->msr & ~0x783f0000ULL;
@@ -1353,6 +1391,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_exception_cb(env_cpu(env), last_pc);
return;
}
/*
@@ -1397,6 +1436,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
if (lev == 1 && books_vhyp_handles_hcall(cpu)) {
cpu->vhyp_class->hypercall(cpu->vhyp, cpu);
powerpc_reset_excp_state(cpu);
+ qemu_plugin_vcpu_hostcall_cb(env_cpu(env), last_pc);
return;
}
if (env->insns_flags2 & PPC2_ISA310) {
@@ -1543,6 +1583,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
powerpc_set_excp_state(cpu, vector, new_msr);
}
+ powerpc_do_plugin_vcpu_interrupt_cb(env_cpu(env), excp, last_pc);
}
#else
static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
--
2.49.1
next prev parent reply other threads:[~2025-09-04 20:49 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-04 20:46 [PATCH v6 00/25] tcg-plugins: add hooks for discontinuities Julian Ganz
2025-09-04 20:46 ` [PATCH v6 01/25] plugins: add types for callbacks related to certain discontinuities Julian Ganz
2025-09-04 20:46 ` [PATCH v6 02/25] plugins: add API for registering discontinuity callbacks Julian Ganz
2025-09-04 20:46 ` [PATCH v6 03/25] plugins: add hooks for new discontinuity related callbacks Julian Ganz
2025-09-22 11:34 ` Philippe Mathieu-Daudé
2025-09-22 20:57 ` Julian Ganz
2025-09-04 20:46 ` [PATCH v6 04/25] contrib/plugins: add plugin showcasing new dicontinuity related API Julian Ganz
2025-09-04 20:46 ` [PATCH v6 05/25] target/alpha: call plugin trap callbacks Julian Ganz
2025-09-04 20:46 ` [PATCH v6 06/25] target/arm: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 07/25] target/avr: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 08/25] target/hppa: " Julian Ganz
2025-09-22 11:38 ` Philippe Mathieu-Daudé
2025-09-22 21:09 ` Julian Ganz
2025-09-04 20:46 ` [PATCH v6 09/25] target/i386: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 10/25] target/loongarch: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 11/25] target/m68k: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 12/25] target/microblaze: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 13/25] target/mips: " Julian Ganz
2025-09-22 11:45 ` Philippe Mathieu-Daudé
2025-09-04 20:46 ` [PATCH v6 14/25] target/openrisc: " Julian Ganz
2025-09-04 20:46 ` Julian Ganz [this message]
2025-09-04 20:46 ` [PATCH v6 16/25] target/riscv: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 17/25] target/rx: " Julian Ganz
2025-09-07 14:20 ` yoshinori.sato
2025-09-04 20:46 ` [PATCH v6 18/25] target/s390x: " Julian Ganz
2025-09-04 20:46 ` [PATCH v6 19/25] target/sh4: " Julian Ganz
2025-09-07 14:20 ` yoshinori.sato
2025-09-04 20:46 ` [PATCH v6 20/25] target/sparc: " Julian Ganz
2025-09-04 20:48 ` Julian Ganz
2025-09-04 20:48 ` [PATCH v6 21/25] target/tricore: " Julian Ganz
2025-09-04 20:48 ` [PATCH v6 22/25] target/xtensa: " Julian Ganz
2025-09-22 11:47 ` Philippe Mathieu-Daudé
2025-09-22 21:12 ` Julian Ganz
2025-09-04 20:48 ` [PATCH v6 23/25] tests: add plugin asserting correctness of discon event's to_pc Julian Ganz
2025-09-21 16:46 ` Alex Bennée
2025-09-22 10:11 ` Julian Ganz
2025-09-22 10:15 ` Daniel P. Berrangé
2025-09-23 20:29 ` Julian Ganz
2025-09-24 15:31 ` Julian Ganz
2025-09-25 10:41 ` Alex Bennée
2025-09-25 12:42 ` Julian Ganz
2025-09-04 20:48 ` [PATCH v6 24/25] tests: add test for double-traps on rv64 Julian Ganz
2025-09-04 20:49 ` [PATCH v6 25/25] tests: add test with interrupted memory accesses " Julian Ganz
2025-09-05 11:38 ` [PATCH v6 00/25] tcg-plugins: add hooks for discontinuities BALATON Zoltan
2025-09-05 12:20 ` Alex Bennée
2025-09-05 13:43 ` Julian Ganz
2025-09-05 19:25 ` BALATON Zoltan
2025-09-05 23:28 ` Julian Ganz
2025-09-07 20:21 ` BALATON Zoltan
2025-09-08 20:51 ` Julian Ganz
2025-09-09 19:48 ` Julian Ganz
2025-09-10 10:06 ` BALATON Zoltan
2025-09-10 11:41 ` Julian Ganz
2025-09-10 12:09 ` Alex Bennée
2025-09-10 15:04 ` BALATON Zoltan
2025-09-22 11:31 ` Philippe Mathieu-Daudé
2025-09-22 20:54 ` Julian Ganz
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d208e845578e8573e85fb6e211f13473e95e9266.1757018626.git.neither@nut.email \
--to=neither@nut.email \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=rathc@linux.ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).