From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org
Subject: Re: [PATCH] target/arm: Fix 64-bit SSRA
Date: Sun, 20 Aug 2023 20:00:37 -0700 [thread overview]
Message-ID: <d2115005-fe67-b934-c2dc-7f2b5f82fd2a@linaro.org> (raw)
In-Reply-To: <20230821022025.397682-1-richard.henderson@linaro.org>
On 8/20/23 19:20, Richard Henderson wrote:
> Typo applied byte-wise shift instead of double-word shift.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1779
Bah. #1737
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/tcg/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
> index b71ac2d0d5..39541ecdf0 100644
> --- a/target/arm/tcg/translate.c
> +++ b/target/arm/tcg/translate.c
> @@ -3053,7 +3053,7 @@ void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
> .vece = MO_32 },
> { .fni8 = gen_ssra64_i64,
> .fniv = gen_ssra_vec,
> - .fno = gen_helper_gvec_ssra_b,
> + .fno = gen_helper_gvec_ssra_d,
> .prefer_i64 = TCG_TARGET_REG_BITS == 64,
> .opt_opc = vecop_list,
> .load_dest = true,
next prev parent reply other threads:[~2023-08-21 3:01 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-21 2:20 [PATCH] target/arm: Fix 64-bit SSRA Richard Henderson
2023-08-21 3:00 ` Richard Henderson [this message]
2023-08-21 6:18 ` Philippe Mathieu-Daudé
2023-08-21 11:56 ` Peter Maydell
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