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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id e1sm2636854pgj.0.2020.06.02.09.34.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Jun 2020 09:34:34 -0700 (PDT) Subject: Re: [PATCH v1 5/9] cputlb: ensure we re-fill the TLB if it has reset To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20200602154624.4460-1-alex.bennee@linaro.org> <20200602154624.4460-6-alex.bennee@linaro.org> From: Richard Henderson Message-ID: Date: Tue, 2 Jun 2020 09:34:32 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20200602154624.4460-6-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, Paolo Bonzini , robhenry@microsoft.com, aaron@os.amperecomputing.com, cota@braap.org, kuhn.chenqun@huawei.com, peter.puhov@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/2/20 8:46 AM, Alex Bennée wrote: > Any write to a device might cause a re-arrangement of memory > triggering a TLB flush and potential re-size of the TLB invalidating > previous entries. This would cause users of qemu_plugin_get_hwaddr() > to see the warning: > > invalid use of qemu_plugin_get_hwaddr > > because of the failed tlb_lookup which should always succeed. We catch > this case by checking to see if the list of entries has been cleared > and if so triggering a re-fill. > > Signed-off-by: Alex Bennée > --- > accel/tcg/cputlb.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c > index eb2cf9de5e6..b7d329f7155 100644 > --- a/accel/tcg/cputlb.c > +++ b/accel/tcg/cputlb.c > @@ -1091,6 +1091,20 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, > MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r, > retaddr); > } > + > + /* > + * The memory_region_dispatch may have triggered a flush/resize > + * so for plugins we need to ensure we have reset the tlb_entry > + * so any later lookup is correct. > + */ > +#ifdef CONFIG_PLUGIN > + if (env_tlb(env)->d[mmu_idx].n_used_entries == 0) { > + int size = op & MO_SIZE; > + tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, > + mmu_idx, retaddr); Ouch. What if the target has a soft tlb fill, so this requires a call into the OS, so this fill actually raises another exception? This will not be happy fun making. I recall I had objections to recording this translation, saying that "we can always get it back again". Clearly I was wrong, and we should just preserve the required CPUTLBEntry details before they're lost by a device. r~