From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@opensource.wdc.com>,
qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL 00/18] riscv-to-apply queue
Date: Thu, 28 Oct 2021 09:54:29 -0700 [thread overview]
Message-ID: <d2a3e189-2070-3c05-c679-12518f16c7b7@linaro.org> (raw)
In-Reply-To: <20211028044342.3070385-1-alistair.francis@opensource.wdc.com>
On 10/27/21 9:43 PM, Alistair Francis wrote:
> From: Alistair Francis<alistair.francis@wdc.com>
>
> The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d:
>
> Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211028
>
> for you to fetch changes up to 344b61e1478c8eb37e81b96f63d8f5071f5a38e1:
>
> target/riscv: remove force HS exception (2021-10-28 14:39:23 +1000)
>
> ----------------------------------------------------------------
> Fifth RISC-V PR for QEMU 6.2
>
> - Use a shared PLIC config helper function
> - Fixup the OpenTitan PLIC configuration
> - Add support for the experimental J extension
> - Update the fmin/fmax handling
> - Fixup VS interrupt forwarding
For avoidance of doubt, I'll wait for an ack from Alistair, whether or not he wants to
update the two min/max patches to Frank's final version.
The code appears to be the same between v4 and v5, but the commit comments are improved,
so this is not something that could be fixed with a second patch.
r~
next prev parent reply other threads:[~2021-10-28 16:56 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 4:43 [PULL 00/18] riscv-to-apply queue Alistair Francis
2021-10-28 4:43 ` [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration Alistair Francis
2021-10-28 4:43 ` [PULL 02/18] hw/riscv: boot: Add a PLIC config string function Alistair Francis
2021-10-28 4:43 ` [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function Alistair Francis
2021-10-28 4:43 ` [PULL 04/18] hw/riscv: microchip_pfsoc: " Alistair Francis
2021-10-28 4:43 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-10-28 4:43 ` [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses Alistair Francis
2021-10-28 4:43 ` [PULL 07/18] target/riscv: Add J-extension into RISC-V Alistair Francis
2021-10-28 4:43 ` [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension Alistair Francis
2021-10-28 4:43 ` [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode Alistair Francis
2021-10-28 4:43 ` [PULL 10/18] target/riscv: Add J extension state description Alistair Francis
2021-10-28 4:43 ` [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs Alistair Francis
2021-10-28 4:43 ` [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alistair Francis
2021-10-28 4:43 ` [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Alistair Francis
2021-10-28 4:43 ` [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on Alistair Francis
2021-10-28 4:43 ` [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin Alistair Francis
2021-10-28 4:43 ` [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax Alistair Francis
2021-10-28 8:22 ` Frank Chang
2021-10-28 11:30 ` Alistair Francis
2021-10-28 14:22 ` Richard Henderson
2021-10-28 21:40 ` Alistair Francis
2021-10-28 4:43 ` [PULL 17/18] target/riscv: fix VS interrupts forwarding to HS Alistair Francis
2021-10-28 4:43 ` [PULL 18/18] target/riscv: remove force HS exception Alistair Francis
2021-10-28 16:54 ` Richard Henderson [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-10-29 14:13 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-11-01 14:02 ` Peter Maydell
2020-11-01 16:27 ` Bin Meng
2020-08-25 18:48 Alistair Francis
2020-08-25 21:24 ` Peter Maydell
2020-08-25 21:21 ` Alistair Francis
2020-08-25 21:49 ` Peter Maydell
2020-08-25 22:30 ` Alistair Francis
2020-08-26 3:21 ` Bin Meng
2020-08-26 9:25 ` Peter Maydell
2020-08-26 10:06 ` Bin Meng
2020-08-27 15:44 ` Alistair Francis
2020-08-29 15:49 ` LIU Zhiwei
2020-08-29 17:30 ` Alistair Francis
2020-08-26 9:28 ` Peter Maydell
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