From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support
Date: Wed, 20 Oct 2021 14:53:34 -0700 [thread overview]
Message-ID: <d2bfacfd-ae4c-0922-a4fa-228613708be6@linaro.org> (raw)
In-Reply-To: <20211019094812.614056-19-frederic.petrot@univ-grenoble-alpes.fr>
On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
> As opposed to the gen_arith and gen_shift generation helpers, the csr insns
> do not have a common prototype, so the choice to generate 32/64 or 128-bit
> helper calls is done in the trans_csrxx functions.
>
> Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 201 ++++++++++++++++++------
> 1 file changed, 156 insertions(+), 45 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-10-20 21:54 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 9:47 [PATCH v3 00/21] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 01/21] memory: change define name for consistency Frédéric Pétrot
2021-10-20 15:07 ` Philippe Mathieu-Daudé
2021-10-19 9:47 ` [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values Frédéric Pétrot
2021-10-19 18:00 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations Frédéric Pétrot
2021-10-19 18:15 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 04/21] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-20 14:08 ` Richard Henderson
2021-10-21 16:22 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-20 14:14 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-20 14:44 ` Richard Henderson
2021-10-22 6:06 ` Frédéric Pétrot
2021-10-19 9:47 ` [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-20 14:57 ` Richard Henderson
2021-10-19 9:47 ` [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part Frédéric Pétrot
2021-10-20 15:09 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 09/21] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-20 15:11 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 10/21] target/riscv: support for 128-bit loads and store Frédéric Pétrot
2021-10-20 17:31 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-10-20 17:47 ` Richard Henderson
2021-10-20 19:18 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-10-20 17:59 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-10-20 19:06 ` Richard Henderson
2021-10-24 22:49 ` Frédéric Pétrot
2021-10-19 9:48 ` [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-10-20 20:15 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 15/21] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-10-20 20:58 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 16/21] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-20 21:38 ` Richard Henderson
2021-10-20 23:03 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-20 21:47 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-20 21:53 ` Richard Henderson [this message]
2021-10-19 9:48 ` [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-10-20 22:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 20/21] target/riscv: adding 128-bit access functions for some csrs Frédéric Pétrot
2021-10-20 23:18 ` Richard Henderson
2021-10-19 9:48 ` [PATCH v3 21/21] target/riscv: support for 128-bit satp Frédéric Pétrot
2021-10-20 23:09 ` Richard Henderson
2021-10-21 11:12 ` Frédéric Pétrot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d2bfacfd-ae4c-0922-a4fa-228613708be6@linaro.org \
--to=richard.henderson@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=fabien.portas@grenoble-inp.org \
--cc=frederic.petrot@univ-grenoble-alpes.fr \
--cc=palmer@dabbelt.com \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).