From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54945) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGPZQ-0006YX-27 for qemu-devel@nongnu.org; Fri, 24 Jun 2016 07:46:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bGPZM-00072k-UV for qemu-devel@nongnu.org; Fri, 24 Jun 2016 07:46:48 -0400 Received: from 16.mo1.mail-out.ovh.net ([178.33.104.224]:53367) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGPZM-00072X-Nm for qemu-devel@nongnu.org; Fri, 24 Jun 2016 07:46:44 -0400 Received: from player758.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 46590FF96B2 for ; Fri, 24 Jun 2016 13:46:43 +0200 (CEST) References: <1466648115-17015-1-git-send-email-andrew@aj.id.au> <1466648115-17015-4-git-send-email-andrew@aj.id.au> <1466734909.23740.125.camel@aj.id.au> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Fri, 24 Jun 2016 13:46:37 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/3] palmetto-bmc: Configure the SCU's hardware strapping register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , Andrew Jeffery Cc: Joel Stanley , QEMU Developers , qemu-arm On 06/24/2016 12:55 PM, Peter Maydell wrote: > On 24 June 2016 at 03:21, Andrew Jeffery wrote: >> On Thu, 2016-06-23 at 18:39 +0100, Peter Maydell wrote: >>> On 23 June 2016 at 03:15, Andrew Jeffery wrote: >>>> >>>> The magic constant configures the following options: >>>> >>>> * 28:27: Configure DRAM size as 256MB >>>> * 26:24: DDR3 SDRAM with CL = 6, CWL = 5 >>>> * 23: Configure 24/48MHz CLKIN >>>> * 22: Disable GPIOE pass-through mode >>>> * 21: Disable GPIOD pass-through mode >>>> * 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses >>>> * 19: Disable ACPI >>>> * 18: Configure 48MHz CLKIN >>>> * 17: Disable BMC 2nd boot watchdog timer >>>> * 16: Decode SuperIO address 0x2E >>>> * 15: VGA Class Code >>>> * 14: Enable LPC dedicated reset pin >>>> * 13:12: Enable SPI Master and SPI Slave to AHB Bridge >>>> * 11:10: Select CPU:AHB ratio = 2:1 >>>> * 9:8: Select 384MHz H-PLL >>>> * 7: Configure MAC#2 for RMII/NCSI >>>> * 6: Configure MAC#1 for RMII/NCSI >>>> * 5: No VGA BIOS ROM >>>> * 4: Boot using 32bit SPI address mode >>>> * 3:2: Select 16MB VGA memory >>>> * 1:0: Boot from SPI flash memory >>> Maybe we should say this in a comment in the code? >> >> The list describes our specific value choices in the register's >> bitfields rather than fully documenting the bitfields and values. If >> you prefer I could switch to the latter and make it a comment, but >> failing that my only thought was if we tweaked the value the comment >> maybe come out of sync. By putting our choices in the commit message >> the description is at least accurate for what was configured at the >> time. > > I'd just like some idea of where the magic number comes > from. At the moment the source code doesn't even have a > reference to a data sheet that would indicate where to look. Yes. I think the HW_STRAP1 register deserves its list of defines. There are some differences between the SOCs. With defines, it will be easier to build and read the values in the platform file. I can do that with a patch I will probably need to unset SPI boot. Thanks, C.