[PATCH v4 0/2] Add memmap and fix bugs for LoongArch

[PATCH v4 0/2] Add memmap and fix bugs for LoongArch

[Xiaojuan Yang]

This series add memmap table and fix extioi, ipi device
emulation for LoongArch virt machine.

Changes for v4:
Add 'reviewed-by' tag in fixing ipi patch, and other changes
are the same as v3.
1. Remove the memmap table patch in this series, it
   will apply until we have more than one machinestate.
2. Using MemTxAttrs' requester_type and requester_id
   to get current cpu index in loongarch extioi regs
   emulation.
   This patch based on: 
   20220927141504.3886314-1-alex.bennee@linaro.org
3. Rewrite the commit message of fixing ipi patch, and 
   add reviewed by tag in the patch.

Changes for v3: 
1. Remove the memmap table patch in this series, it
   will apply until we have more than one machinestate.
2. Using MemTxAttrs' requester_type and requester_id
   to get current cpu index in loongarch extioi regs
   emulation.
   This patch based on: 
   20220927141504.3886314-1-alex.bennee@linaro.org
3. Rewrite the commit message of fixing ipi patch, and 
   this patch has been reviewed.

Changes for v2:
1. Adjust the position of 'PLATFORM' element in memmap table

Changes for v1: 
1. Add memmap table for LoongArch virt machine
2. Fix LoongArch extioi function
3. Fix LoongArch ipi device emulation

Xiaojuan Yang (2):
  hw/intc: Fix LoongArch extioi function
  hw/intc: Fix LoongArch ipi device emulation

 hw/intc/loongarch_extioi.c      | 51 +++++++++++++++++++--------------
 hw/intc/loongarch_ipi.c         |  1 -
 hw/intc/trace-events            |  2 +-
 target/loongarch/iocsr_helper.c | 16 +++++------
 4 files changed, 38 insertions(+), 32 deletions(-)

-- 
2.31.1

[PATCH v4 1/2] hw/intc: Fix LoongArch extioi function

[Xiaojuan Yang]

1.When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the index of 's->coreisr' is
current cpu number. Using MemTxAttrs' requester_type and id
to get the cpu index.
2.Remove the unused extioi system memory region and we only
support the extioi iocsr memory region now.

Based-on: <20220927141504.3886314-1-alex.bennee@linaro.org>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 hw/intc/loongarch_extioi.c      | 51 +++++++++++++++++++--------------
 hw/intc/trace-events            |  2 +-
 target/loongarch/iocsr_helper.c | 16 +++++------
 3 files changed, 38 insertions(+), 31 deletions(-)

diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
index 22803969bc..e94bc91565 100644
--- a/hw/intc/loongarch_extioi.c
+++ b/hw/intc/loongarch_extioi.c
@@ -17,7 +17,6 @@
 #include "migration/vmstate.h"
 #include "trace.h"
 
-
 static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level)
 {
     int ipnum, cpu, found, irq_index, irq_mask;
@@ -68,44 +67,49 @@ static void extioi_setirq(void *opaque, int irq, int level)
     extioi_update_irq(s, irq, level);
 }
 
-static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+static MemTxResult extioi_readw(void *opaque, hwaddr addr, uint64_t *data,
+                                unsigned size, MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     unsigned long offset = addr & 0xffff;
-    uint32_t index, cpu, ret = 0;
+    uint32_t index, cpu;
 
     switch (offset) {
     case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
         index = (offset - EXTIOI_NODETYPE_START) >> 2;
-        ret = s->nodetype[index];
+        *data = s->nodetype[index];
         break;
     case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
         index = (offset - EXTIOI_IPMAP_START) >> 2;
-        ret = s->ipmap[index];
+        *data = s->ipmap[index];
         break;
     case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
         index = (offset - EXTIOI_ENABLE_START) >> 2;
-        ret = s->enable[index];
+        *data = s->enable[index];
         break;
     case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
         index = (offset - EXTIOI_BOUNCE_START) >> 2;
-        ret = s->bounce[index];
+        *data = s->bounce[index];
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
-        ret = s->coreisr[cpu][index];
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        if (attrs.requester_type != MTRT_CPU) {
+            return MEMTX_ACCESS_ERROR;
+        }
+        cpu = attrs.requester_id;
+        *data = s->coreisr[cpu][index];
         break;
     case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
         index = (offset - EXTIOI_COREMAP_START) >> 2;
-        ret = s->coremap[index];
+        *data = s->coremap[index];
         break;
     default:
         break;
     }
 
-    trace_loongarch_extioi_readw(addr, ret);
-    return ret;
+    trace_loongarch_extioi_readw(addr, *data);
+    return MEMTX_OK;
 }
 
 static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
@@ -127,8 +131,9 @@ static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
     }
 }
 
-static void extioi_writew(void *opaque, hwaddr addr,
-                          uint64_t val, unsigned size)
+static MemTxResult extioi_writew(void *opaque, hwaddr addr,
+                          uint64_t val, unsigned size,
+                          MemTxAttrs attrs)
 {
     LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
     int i, cpu, index, old_data, irq;
@@ -183,8 +188,12 @@ static void extioi_writew(void *opaque, hwaddr addr,
         s->bounce[index] = val;
         break;
     case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
-        index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
-        cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+        index = (offset - EXTIOI_COREISR_START) >> 2;
+        /* using attrs to get current cpu index */
+        if (attrs.requester_type != MTRT_CPU) {
+            return MEMTX_ACCESS_ERROR;
+        }
+        cpu = attrs.requester_id;
         old_data = s->coreisr[cpu][index];
         s->coreisr[cpu][index] = old_data & ~val;
         /* write 1 to clear interrrupt */
@@ -231,11 +240,12 @@ static void extioi_writew(void *opaque, hwaddr addr,
     default:
         break;
     }
+    return MEMTX_OK;
 }
 
 static const MemoryRegionOps extioi_ops = {
-    .read = extioi_readw,
-    .write = extioi_writew,
+    .read_with_attrs = extioi_readw,
+    .write_with_attrs = extioi_writew,
     .impl.min_access_size = 4,
     .impl.max_access_size = 4,
     .valid.min_access_size = 4,
@@ -284,9 +294,6 @@ static void loongarch_extioi_instance_init(Object *obj)
             qdev_init_gpio_out(DEVICE(obj), &s->parent_irq[cpu][pin], 1);
         }
     }
-    memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops,
-                          s, "extioi_system_mem", 0x900);
-    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_system_mem);
 }
 
 static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 0a90c1cdec..e505d8a2b8 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -306,6 +306,6 @@ loongarch_msi_set_irq(int irq_num) "set msi irq %d"
 
 # loongarch_extioi.c
 loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
-loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
+loongarch_extioi_readw(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
 
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
index 0e9c537dc7..d3aac362ff 100644
--- a/target/loongarch/iocsr_helper.c
+++ b/target/loongarch/iocsr_helper.c
@@ -17,51 +17,51 @@
 uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldub(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_lduw(&env->address_space_iocsr, r_addr,
-                              MEMTXATTRS_UNSPECIFIED, NULL);
+                              MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldl(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldq(&env->address_space_iocsr, r_addr,
-                             MEMTXATTRS_UNSPECIFIED, NULL);
+                             MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 void helper_iocsrwr_b(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stb(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 void helper_iocsrwr_h(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stw(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 void helper_iocsrwr_w(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stl(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
 
 void helper_iocsrwr_d(CPULoongArchState *env, target_ulong w_addr,
                       target_ulong val)
 {
     address_space_stq(&env->address_space_iocsr, w_addr,
-                      val, MEMTXATTRS_UNSPECIFIED, NULL);
+                      val, MEMTXATTRS_CPU(env_cpu(env)), NULL);
 }
-- 
2.31.1

Re: [PATCH v4 1/2] hw/intc: Fix LoongArch extioi function

[Richard Henderson]

On 9/30/22 02:51, Xiaojuan Yang wrote:
> 1.When cpu read or write extioi COREISR reg, it should access
> the reg belonged to itself, so the index of 's->coreisr' is
> current cpu number. Using MemTxAttrs' requester_type and id
> to get the cpu index.
> 2.Remove the unused extioi system memory region and we only
> support the extioi iocsr memory region now.
> 
> Based-on:<20220927141504.3886314-1-alex.bennee@linaro.org>
> Signed-off-by: Xiaojuan Yang<yangxiaojuan@loongson.cn>
> ---
>   hw/intc/loongarch_extioi.c      | 51 +++++++++++++++++++--------------
>   hw/intc/trace-events            |  2 +-
>   target/loongarch/iocsr_helper.c | 16 +++++------
>   3 files changed, 38 insertions(+), 31 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

For future reference, the Based-on: tag belongs in the cover letter.


r~

[PATCH v4 2/2] hw/intc: Fix LoongArch ipi device emulation

[Xiaojuan Yang]

In ipi_send function, it should not to set irq before
writing data to dest cpu iocsr space, as the irq will
trigger after data writing.
When call this function 'address_space_stl()', it will
trigger loongarch_ipi_writel(), the addr arg is 0x1008
('CORE_SET_OFF'), and qemu_irq_raise will be called in
this case.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 hw/intc/loongarch_ipi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 4f3c58f872..aa4bf9eb74 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -88,7 +88,6 @@ static void ipi_send(uint64_t val)
     cs = qemu_get_cpu(cpuid);
     cpu = LOONGARCH_CPU(cs);
     env = &cpu->env;
-    loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);
     address_space_stl(&env->address_space_iocsr, 0x1008,
                       data, MEMTXATTRS_UNSPECIFIED, NULL);
 
-- 
2.31.1

Re: [PATCH v4 0/2] Add memmap and fix bugs for LoongArch

[gaosong]

在 2022/9/30 17:51, Xiaojuan Yang 写道:
> This series add memmap table and fix extioi, ipi device
> emulation for LoongArch virt machine.
>
> Changes for v4:
> Add 'reviewed-by' tag in fixing ipi patch, and other changes
> are the same as v3.
> 1. Remove the memmap table patch in this series, it
>     will apply until we have more than one machinestate.
> 2. Using MemTxAttrs' requester_type and requester_id
>     to get current cpu index in loongarch extioi regs
>     emulation.
>     This patch based on:
>     20220927141504.3886314-1-alex.bennee@linaro.org
> 3. Rewrite the commit message of fixing ipi patch, and
>     add reviewed by tag in the patch.
>
> Changes for v3:
> 1. Remove the memmap table patch in this series, it
>     will apply until we have more than one machinestate.
> 2. Using MemTxAttrs' requester_type and requester_id
>     to get current cpu index in loongarch extioi regs
>     emulation.
>     This patch based on:
>     20220927141504.3886314-1-alex.bennee@linaro.org
> 3. Rewrite the commit message of fixing ipi patch, and
>     this patch has been reviewed.
>
> Changes for v2:
> 1. Adjust the position of 'PLATFORM' element in memmap table
>
> Changes for v1:
> 1. Add memmap table for LoongArch virt machine
> 2. Fix LoongArch extioi function
> 3. Fix LoongArch ipi device emulation
>
> Xiaojuan Yang (2):
>    hw/intc: Fix LoongArch extioi function
>    hw/intc: Fix LoongArch ipi device emulation
>
>   hw/intc/loongarch_extioi.c      | 51 +++++++++++++++++++--------------
>   hw/intc/loongarch_ipi.c         |  1 -
>   hw/intc/trace-events            |  2 +-
>   target/loongarch/iocsr_helper.c | 16 +++++------
>   4 files changed, 38 insertions(+), 32 deletions(-)
Applied to loongarch-next.

Thanks.
Song Gao