From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41135) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLbOT-000701-NB for qemu-devel@nongnu.org; Fri, 08 Jul 2016 15:24:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLbOO-0006LO-NL for qemu-devel@nongnu.org; Fri, 08 Jul 2016 15:24:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47411) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLbOO-0006L0-Hp for qemu-devel@nongnu.org; Fri, 08 Jul 2016 15:24:52 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8E4BC6315E for ; Fri, 8 Jul 2016 19:24:51 +0000 (UTC) References: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> <1467990099-27853-3-git-send-email-dgilbert@redhat.com> <20160708185932.GO4131@thinpad.lan.raisama.net> From: Paolo Bonzini Message-ID: Date: Fri, 8 Jul 2016 21:24:47 +0200 MIME-Version: 1.0 In-Reply-To: <20160708185932.GO4131@thinpad.lan.raisama.net> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v4 2/5] x86: Allow physical address bits to be set List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost , "Dr. David Alan Gilbert (git)" Cc: qemu-devel@nongnu.org, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com On 08/07/2016 20:59, Eduardo Habkost wrote: > > + if (env->features[FEAT_1_EDX] & CPUID_PSE36) { > > + cpu->phys_bits =3D 36; > > + } else { > > + cpu->phys_bits =3D 32; >=20 > But TCG_PHYS_ADDR_BITS is still 36. Does this mean TCG > reserved-bit handling is broken if pse36 is disabled? This makes sense as a default, apparently if you don't have PSE36 but=20 you have phys_bits > 32, Windows complains: commit 45fd08effd461f85d0480d3b8f85a07751fc55b3 Author: aurel32 Date: Tue Oct 14 19:20:52 2008 +0000 target-i386: Add Core Duo Definition =20 This patch adds a CPU definition for the Core Duo CPU. I tried to resemble the original as closely as possible and document what featur= es are missing still. This patch enables the use of a recent CPU definit= ion on 32 bit platforms. =20 It also fixes two issues that went along the line: =20 - invalid xlevel in core2duo spec While looking though the CPUIDs again, I found that xlevel is actua= lly 8. =20 - non-PSE36 support The CoreDuo CPUID does not expose the PSE36 capability, but CPUID 0x80000008 is tied to 36 bits. This broke Windows XP installation for me, so I just set it to 32 bits width when PSE36 is not available. Th= e original CPU also exposes 32 bit width in CPUID 0x80000008. =20 Signed-off-by: Alexander Graf Signed-off-by: Aurelien Jarno =20 git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5488 c046a42c-6f= e2-441c-8c8c-71466251a162 As long as it's overridable I guess it's fine... Paolo