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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id iz10-20020a170902ef8a00b0019c901b35ecsm4949454plb.106.2023.02.27.10.32.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Feb 2023 10:32:17 -0800 (PST) Message-ID: Date: Mon, 27 Feb 2023 08:32:12 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [RFC PATCH 10/43] target/loongarch: Implement vaddw/vsubw To: gaosong , qemu-devel@nongnu.org References: <20221224081633.4185445-1-gaosong@loongson.cn> <20221224081633.4185445-11-gaosong@loongson.cn> <268ef762-fce5-ca47-d5f7-bd60955a3a0f@linaro.org> <1ad204fc-8f7e-0f1c-e8f6-163d11f3880b@linaro.org> <5ac3c25f-8d4b-6aa3-5bc2-2b3abc22dce8@linaro.org> <32723bb0-17fe-cbd5-73f1-99cbcfbf73aa@loongson.cn> Content-Language: en-US From: Richard Henderson In-Reply-To: <32723bb0-17fe-cbd5-73f1-99cbcfbf73aa@loongson.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/27/23 02:54, gaosong wrote: > > 在 2023/2/27 下午5:20, Richard Henderson 写道: >> On 2/26/23 23:14, gaosong wrote: >>> like this: >>> the vece is MO_32. >>> static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) >>> { >>>      TCGv_vec t1 = tcg_temp_new_vec_matching(a); >>>      TCGv_vec t2 = tcg_temp_new_vec_matching(b); >>>      int halfbits = 4 << vece; >>>      tcg_gen_shli_vec(vece, t1, a, halfbits); >>>      tcg_gen_shri_vec(vece, t1, t1, halfbits); >>> >>>      tcg_gen_shli_vec(vece, t2, b,  halfbits); >>>      tcg_gen_shri_vec(vece, t2, t2, halfbits); >>> >>>      tcg_gen_add_vec(vece, t, t1, t2); >>> >>>      tcg_temp_free_vec(t1); >>>      tcg_temp_free_vec(t2); >>> } >>> ... >>>         op[MO_16]; >>>          { >>>              .fniv = gen_vaddwev_s, >>>              .fno = gen_helper_vaddwev_w_h, >>>              .opt_opc = vecop_list, >>>              .vece = MO_32 >>>          }, >>> ... >>> TRANS(vaddwev_w_h, gvec_vvv, MO_16, gvec_vaddwev_s) >>> >>> input :     0x ffff fffe ffff fffe  ffff fffe ffff fffe  + 0 >>> output :    0x 0000 fffe 0000 fffe  0000 fffe 0000 fffe >>> correct is  0xffffffffefffffffefffffffe       ffff fffe. >> >> sari above, not shri, for sign-extension. >> >> > Got it. > > and how to  sign-extend  the odd  element  of vector? For the odd elements, you omit the shli, because the odd element is already at the most significant end of the wider element. r~