From: Richard Henderson <richard.henderson@linaro.org>
To: Stafford Horne <shorne@gmail.com>,
QEMU Development <qemu-devel@nongnu.org>
Cc: davidsondfgl@gmail.com, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register
Date: Sun, 1 Jul 2018 07:19:52 -0700 [thread overview]
Message-ID: <d336819e-ab5c-2c36-e1c2-9ac1b306c8ae@linaro.org> (raw)
In-Reply-To: <20180701081245.14357-1-shorne@gmail.com>
On 07/01/2018 01:12 AM, Stafford Horne wrote:
> The interrupt controller mask register (PICMR) allows writing any value
> to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt
> writing a 1 unmasks (enables) the the interrupt.
>
> For some reason the old code was or'ing the write values to the PICMR
> meaning it was not possible to ever mask a interrupt once it was
> enabled.
>
> I have tested this by running linux 4.18 and my regular checks, I don't
> see any issues.
>
> Reported-by: Davidson Francis <davidsondfgl@gmail.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> target/openrisc/sys_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
prev parent reply other threads:[~2018-07-01 14:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-01 8:12 [Qemu-devel] [PATCH] target/openrisc: Fix writes to interrupt mask register Stafford Horne
2018-07-01 14:19 ` Richard Henderson [this message]
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