From: Paul Clarke <pc@us.ibm.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [PATCH v2 2/2] ppc: Add support for 'mffsce' instruction
Date: Tue, 17 Sep 2019 16:49:56 -0500 [thread overview]
Message-ID: <d38484cb-8a78-c58c-6ab4-921c9450a346@us.ibm.com> (raw)
In-Reply-To: <77049b6d-92cd-014f-6151-fb8dc4b032c9@linaro.org>
On 9/17/19 3:46 PM, Richard Henderson wrote:
> On 9/16/19 1:02 PM, Paul A. Clarke wrote:
>> From: "Paul A. Clarke" <pc@us.ibm.com>
>>
>> ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR)
>> instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl.
>> This patch adds support for 'mffsce' instruction.
>>
>> 'mffsce' is identical to 'mffs', except that it also clears the exception
>> enable bits in the FPSCR.
>>
>> On CPUs without support for 'mffsce' (below ISA 3.0), the
>> instruction will execute identically to 'mffs'.
>>
>> Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
>> ---
>> v2: no changes.
>>
>> target/ppc/translate/fp-impl.inc.c | 30 ++++++++++++++++++++++++++++++
>> target/ppc/translate/fp-ops.inc.c | 2 ++
>> 2 files changed, 32 insertions(+)
>
> Didn't I already give a
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> for this?
You did. Sorry for the confusion. I wasn't sure whether to resend or not, given the dependence on the other patch and David said he would be waiting for the respin.
PC
next prev parent reply other threads:[~2019-09-17 21:51 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-16 17:02 [Qemu-devel] [PATCH v2 2/2] ppc: Add support for 'mffsce' instruction Paul A. Clarke
2019-09-17 20:46 ` Richard Henderson
2019-09-17 21:49 ` Paul Clarke [this message]
2019-09-18 0:47 ` David Gibson
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