Re: [PATCH v4 0/5] RISC-V: NEORV32 CPU, peripherials, and machine

[Thomas Huth <thuth@redhat.com>]

On 09/11/2025 20.15, Michael Levit wrote:
> 
> This v4 reworks the initial NEORV32 submissions.
> 
> The series introduces:
>    * a minimal NEORV32 RV32 CPU type and vendor CSR hook,
>    * the SYSINFO MMIO block,
>    * a small UART device,
>    * an SPI controller with command-mode chip-select,
>    * and the 'neorv32' RISC-V board wiring the above, plus docs.
> 
> Tested by booting the NEORV32 bootloader as -bios and chaining into a
> Hello World from an MTD-backed SPI flash image, with UART on stdio.

  Hi!

Are these binaries available publically somewhere on the internet? If so, 
could you please add a test in tests/functional/riscv32 that make sure that 
the machine is basically working, so we don't face any regressions in the 
future?

  Thanks,
   Thomas