From: Dongli Zhang <dongli.zhang@oracle.com>
To: Paolo Bonzini <pbonzini@redhat.com>, qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [Regression] Re: [PULL 35/35] qom: reverse order of instance_post_init calls
Date: Mon, 23 Jun 2025 09:56:14 -0700 [thread overview]
Message-ID: <d429b6f5-b59c-4884-b18f-8db71cb8dc7b@oracle.com> (raw)
In-Reply-To: <20250520110530.366202-36-pbonzini@redhat.com>
This commit may broken the "vendor=" configuration.
For instance, the hypervisor CPU vendor is AMD.
I am going to use "-cpu Skylake-Server,vendor=GenuineIntel".
Because of the commit, the vendor is still AMD.
[root@vm ~]# cpuid -1 -l 0x0
CPU:
vendor_id = "AuthenticAMD"
If I revert this patch, the vendor because the expected Intel.
[root@vm ~]# cpuid -1 -l 0x0
CPU:
vendor_id = "GenuineIntel"
Thank you very much!
Dongli Zhang
On 5/20/25 4:05 AM, Paolo Bonzini wrote:
> Currently, the instance_post_init calls are performed from the leaf
> class and all the way up to Object. This is incorrect because the
> leaf class cannot observe property values applied by the superclasses;
> for example, a compat property will be set on a device *after*
> the class's post_init callback has run.
>
> In particular this makes it impossible for implementations of
> accel_cpu_instance_init() to operate based on the actual values of
> the properties, though it seems that cxl_dsp_instance_post_init and
> rp_instance_post_init might have similar issues.
>
> Follow instead the same order as instance_init, starting with Object
> and running the child class's instance_post_init after the parent.
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> include/qom/object.h | 3 ++-
> qom/object.c | 8 ++++----
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/include/qom/object.h b/include/qom/object.h
> index 1d5b0337242..26df6137b91 100644
> --- a/include/qom/object.h
> +++ b/include/qom/object.h
> @@ -445,7 +445,8 @@ struct Object
> * class will have already been initialized so the type is only responsible
> * for initializing its own members.
> * @instance_post_init: This function is called to finish initialization of
> - * an object, after all @instance_init functions were called.
> + * an object, after all @instance_init functions were called, as well as
> + * @instance_post_init functions for the parent classes.
> * @instance_finalize: This function is called during object destruction. This
> * is called before the parent @instance_finalize function has been called.
> * An object should only free the members that are unique to its type in this
> diff --git a/qom/object.c b/qom/object.c
> index 7b013f40a0c..1856bb36c74 100644
> --- a/qom/object.c
> +++ b/qom/object.c
> @@ -431,13 +431,13 @@ static void object_init_with_type(Object *obj, TypeImpl *ti)
>
> static void object_post_init_with_type(Object *obj, TypeImpl *ti)
> {
> - if (ti->instance_post_init) {
> - ti->instance_post_init(obj);
> - }
> -
> if (type_has_parent(ti)) {
> object_post_init_with_type(obj, type_get_parent(ti));
> }
> +
> + if (ti->instance_post_init) {
> + ti->instance_post_init(obj);
> + }
> }
>
> bool object_apply_global_props(Object *obj, const GPtrArray *props,
next prev parent reply other threads:[~2025-06-23 16:56 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-20 11:04 [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Paolo Bonzini
2025-05-20 11:04 ` [PULL 01/35] i386/tcg: Make CPUID_HT and CPUID_EXT3_CMP_LEG supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 02/35] i386/hvf: Make CPUID_HT supported Paolo Bonzini
2025-05-20 11:04 ` [PULL 03/35] hw/pci-host/gt64120: Fix endianness handling Paolo Bonzini
2025-05-20 11:04 ` [PULL 04/35] hw/pci-host: Remove unused pci_host_data_be_ops Paolo Bonzini
2025-05-20 11:05 ` [PULL 05/35] qapi/misc-target: Rename SGXEPCSection to SgxEpcSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 06/35] qapi/misc-target: Rename SGXInfo to SgxInfo Paolo Bonzini
2025-05-20 11:05 ` [PULL 07/35] qapi/misc-target: Fix the doc related SGXEPCSection Paolo Bonzini
2025-05-20 11:05 ` [PULL 08/35] qapi/misc-target: Fix the doc to distinguish query-sgx and query-sgx-capabilities Paolo Bonzini
2025-05-20 11:05 ` [PULL 09/35] hw/riscv: acpi: only create RHCT MMU entry for supported types Paolo Bonzini
2025-05-20 11:05 ` [PULL 10/35] target/riscv: assert argument to set_satp_mode_max_supported is valid Paolo Bonzini
2025-05-20 11:05 ` [PULL 11/35] target/riscv: cpu: store max SATP mode as a single integer Paolo Bonzini
2025-05-20 11:05 ` [PULL 12/35] target/riscv: update max_satp_mode based on QOM properties Paolo Bonzini
2025-05-20 11:05 ` [PULL 13/35] target/riscv: remove supported from RISCVSATPMap Paolo Bonzini
2025-05-20 11:05 ` [PULL 14/35] target/riscv: move satp_mode.{map, init} out of CPUConfig Paolo Bonzini via
2025-05-20 11:05 ` [PULL 15/35] target/riscv: introduce RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 16/35] target/riscv: store RISCVCPUDef struct directly in the class Paolo Bonzini
2025-05-20 11:05 ` [PULL 17/35] target/riscv: merge riscv_cpu_class_init with the class_base function Paolo Bonzini
2025-05-20 11:05 ` [PULL 18/35] target/riscv: move RISCVCPUConfig fields to a header file Paolo Bonzini
2025-05-20 11:05 ` [PULL 19/35] target/riscv: include default value in cpu_cfg_fields.h.inc Paolo Bonzini
2025-05-20 11:05 ` [PULL 20/35] target/riscv: add more RISCVCPUDef fields Paolo Bonzini
2025-05-20 11:05 ` [PULL 21/35] target/riscv: convert abstract CPU classes to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 22/35] target/riscv: convert profile CPU models " Paolo Bonzini
2025-05-20 11:05 ` [PULL 23/35] target/riscv: convert bare " Paolo Bonzini
2025-05-20 11:05 ` [PULL 24/35] target/riscv: convert dynamic " Paolo Bonzini
2025-05-20 11:05 ` [PULL 25/35] target/riscv: convert SiFive E " Paolo Bonzini
2025-05-20 11:05 ` [PULL 26/35] target/riscv: convert ibex " Paolo Bonzini
2025-05-20 11:05 ` [PULL 27/35] target/riscv: convert SiFive U " Paolo Bonzini
2025-05-20 11:05 ` [PULL 28/35] target/riscv: th: make CSR insertion test a bit more intuitive Paolo Bonzini
2025-05-20 11:05 ` [PULL 29/35] target/riscv: generalize custom CSR functionality Paolo Bonzini
2025-05-20 11:05 ` [PULL 30/35] target/riscv: convert THead C906 to RISCVCPUDef Paolo Bonzini
2025-05-20 11:05 ` [PULL 31/35] target/riscv: convert TT Ascalon " Paolo Bonzini
2025-05-20 11:05 ` [PULL 32/35] target/riscv: convert Ventana V1 " Paolo Bonzini
2025-05-20 11:05 ` [PULL 33/35] target/riscv: convert Xiangshan Nanhu " Paolo Bonzini
2025-05-20 11:05 ` [PULL 34/35] target/riscv: remove .instance_post_init Paolo Bonzini
2025-05-20 11:05 ` [PULL 35/35] qom: reverse order of instance_post_init calls Paolo Bonzini
2025-06-23 16:56 ` Dongli Zhang [this message]
2025-06-24 8:57 ` [Regression] " Zhao Liu
2025-06-30 15:22 ` Zhao Liu
2025-07-01 6:50 ` Xiaoyao Li
2025-07-02 6:54 ` Philippe Mathieu-Daudé
2025-07-02 7:56 ` Zhao Liu
2025-07-02 11:42 ` Xiaoyao Li
2025-07-02 12:12 ` Paolo Bonzini
2025-07-02 13:24 ` Xiaoyao Li
2025-07-02 18:54 ` Paolo Bonzini
2025-07-03 1:03 ` Xiaoyao Li
2025-07-03 3:08 ` Zhao Liu
2025-07-03 3:36 ` Xiaoyao Li
2025-07-03 4:51 ` Paolo Bonzini
2025-07-07 15:41 ` Paolo Bonzini
2025-07-02 12:06 ` Paolo Bonzini
2025-05-21 14:06 ` [PULL 00/35] RISCV, i386, endianness fixes for 2025-05-20 Stefan Hajnoczi
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