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[93.34.153.63]) by smtp.gmail.com with ESMTPSA id c6sm7415579wma.25.2019.06.27.04.35.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Jun 2019 04:35:13 -0700 (PDT) To: Stefan Brankovic , qemu-devel@nongnu.org References: <1561632985-24866-1-git-send-email-stefan.brankovic@rt-rk.com> <1561632985-24866-9-git-send-email-stefan.brankovic@rt-rk.com> From: Richard Henderson Openpgp: preference=signencrypt Message-ID: Date: Thu, 27 Jun 2019 13:35:12 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1561632985-24866-9-git-send-email-stefan.brankovic@rt-rk.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: Re: [Qemu-devel] [PATCH v4 08/13] tcg: Add opcodes for vector vmrgh instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hsp.cat7@gmail.com, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/27/19 12:56 PM, Stefan Brankovic wrote: > +void HELPER(gvec_vmrgh8)(void *d, void *a, void *b, uint32_t desc) > +{ > + intptr_t oprsz = simd_oprsz(desc); > + intptr_t i; > + > + for (i = 0; i < (oprsz / 2); i += sizeof(uint8_t)) { > + uint8_t aa = *(uint8_t *)(a + 8 * sizeof(uint8_t) + i); > + uint8_t bb = *(uint8_t *)(b + 8 * sizeof(uint8_t) + i); > + *(uint8_t *)(d + 2 * i) = bb; > + *(uint8_t *)(d + 2 * i + sizeof(uint8_t)) = aa; > + } > + clear_high(d, oprsz, desc); > +} I tried this while developing the ARM SVE code. The problem is that the vector element numbering differs for each host. So while you may be able to get the correct results out of x86, you'll the the wrong answers when you run this same code on a big-endian host. The same goes for the INDEX_OP_vmrgh_vec opcode you introduced. r~