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[93.96.11.101]) by smtp.gmail.com with ESMTPSA id n19-20020a1c7213000000b003f4268f51f5sm2520982wmc.0.2023.05.08.06.41.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 06:42:04 -0700 (PDT) Message-ID: Date: Mon, 8 May 2023 14:41:53 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v4 14/57] tcg/i386: Add have_atomic16 Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, git@xen0n.name, gaosong@loongson.cn, philmd@linaro.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org References: <20230503070656.1746170-1-richard.henderson@linaro.org> <20230503070656.1746170-15-richard.henderson@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -38 X-Spam_score: -3.9 X-Spam_bar: --- X-Spam_report: (-3.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.802, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/5/23 11:34, Peter Maydell wrote: > On Wed, 3 May 2023 at 08:10, Richard Henderson > wrote: >> >> Notice when Intel or AMD have guaranteed that vmovdqa is atomic. >> The new variable will also be used in generated code. >> >> Signed-off-by: Richard Henderson >> --- >> include/qemu/cpuid.h | 18 ++++++++++++++++++ >> tcg/i386/tcg-target.h | 1 + >> tcg/i386/tcg-target.c.inc | 27 +++++++++++++++++++++++++++ >> 3 files changed, 46 insertions(+) >> >> diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h >> index 1451e8ef2f..35325f1995 100644 >> --- a/include/qemu/cpuid.h >> +++ b/include/qemu/cpuid.h >> @@ -71,6 +71,24 @@ >> #define bit_LZCNT (1 << 5) >> #endif >> >> +/* >> + * Signatures for different CPU implementations as returned from Leaf 0. >> + */ >> + >> +#ifndef signature_INTEL_ecx >> +/* "Genu" "ineI" "ntel" */ >> +#define signature_INTEL_ebx 0x756e6547 >> +#define signature_INTEL_edx 0x49656e69 >> +#define signature_INTEL_ecx 0x6c65746e >> +#endif >> + >> +#ifndef signature_AMD_ecx >> +/* "Auth" "enti" "cAMD" */ >> +#define signature_AMD_ebx 0x68747541 >> +#define signature_AMD_edx 0x69746e65 >> +#define signature_AMD_ecx 0x444d4163 >> +#endif > >> @@ -4024,6 +4025,32 @@ static void tcg_target_init(TCGContext *s) >> have_avx512dq = (b7 & bit_AVX512DQ) != 0; >> have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0; >> } >> + >> + /* >> + * The Intel SDM has added: >> + * Processors that enumerate support for Intel® AVX >> + * (by setting the feature flag CPUID.01H:ECX.AVX[bit 28]) >> + * guarantee that the 16-byte memory operations performed >> + * by the following instructions will always be carried >> + * out atomically: >> + * - MOVAPD, MOVAPS, and MOVDQA. >> + * - VMOVAPD, VMOVAPS, and VMOVDQA when encoded with VEX.128. >> + * - VMOVAPD, VMOVAPS, VMOVDQA32, and VMOVDQA64 when encoded >> + * with EVEX.128 and k0 (masking disabled). >> + * Note that these instructions require the linear addresses >> + * of their memory operands to be 16-byte aligned. >> + * >> + * AMD has provided an even stronger guarantee that processors >> + * with AVX provide 16-byte atomicity for all cachable, >> + * naturally aligned single loads and stores, e.g. MOVDQU. >> + * >> + * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 >> + */ >> + if (have_avx1) { >> + __cpuid(0, a, b, c, d); >> + have_atomic16 = (c == signature_INTEL_ecx || >> + c == signature_AMD_ecx); >> + } > > If the signature is 3 words why are we only checking one here ? Because one is sufficient. I don't know why the signature is 3 words and not 1. r~