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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c8d7e5910fsm763725a91.11.2024.06.25.23.18.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jun 2024 23:18:27 -0700 (PDT) Message-ID: Date: Wed, 26 Jun 2024 14:18:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 0/6] target/riscv: Add support for Control Transfer Records Ext. To: Rajnesh Kanwal , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, beeman@rivosinc.com, tech-control-transfer-records@lists.riscv.org References: <20240619152708.135991-1-rkanwal@rivosinc.com> Content-Language: en-US From: Jason Chien In-Reply-To: <20240619152708.135991-1-rkanwal@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=jason.chien@sifive.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Rajnesh, On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote: > This series enables Control Transfer Records extension support on riscv > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > The Extension has been stable and the latest release can be found here [0] > > CTR extension depends on couple of other extensions: > > 1. S[m|s]csrind : The indirect CSR extension [1] which defines additional > ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of > RISC-V CSR address space. CTR access ctrsource, ctrtartget and ctrdata > CSRs using sscsrind extension. There is no dependency on Smcsrind. > > 2. Smstateen: The mstateen bit[54] controls the access to the CTR ext to > S-mode. This bit is missing in write_mstateen0(), write_mstateen0h(), write_hstateen0() and write_hstateen0h(). > > 3. Sscofpmf: Counter overflow and privilege mode filtering. [2] > > The series is based on Smcdeleg/Ssccfg counter delegation extension [3] > patches. CTR itself doesn't depend on counter delegation support. This > rebase is basically to include the Smcsrind patches. > > Due to the dependency of these extensions, the following extensions must be > enabled to use the control transfer records feature. > > "smstateen=true,sscofpmf=true,smcsrind=true,sscsrind=true,smctr=true,ssctr=true" > > Here is the link to a quick guide [5] to setup and run a basic perf demo on > Linux to use CTR Ext. > > The Qemu patches can be found here: > https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream_v2 > > The opensbi patch can be found here: > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 > > The Linux kernel patches can be found here: > https://github.com/rajnesh-kanwal/linux/tree/ctr_upstream_v2 > > [0]: https://github.com/riscv/riscv-control-transfer-records/release > [1]: https://github.com/riscv/riscv-indirect-csr-access > [2]: https://github.com/riscvarchive/riscv-count-overflow/tree/main > [3]: https://github.com/riscv/riscv-smcdeleg-ssccfg > [4]: https://lore.kernel.org/all/20240217000134.3634191-1-atishp@rivosinc.com/ > [5]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine > > Changelog: > > v2: Lots of improvements based on Jason Chien's feedback including: Thank you for mentioning my name! > - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz. > - Fixed and added more CTR extension enable checks. > - Fixed CTR CSR predicate functions. > - Fixed external trap xTE bit checks. > - One fix in freeze function for VS-mode. > - Lots of minor code improvements. > - Added checks in sctrclr instruction helper. > > v1: > - https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream > > > Rajnesh Kanwal (6): > target/riscv: Remove obsolete sfence.vm instruction > target/riscv: Add Control Transfer Records CSR definitions. > target/riscv: Add support for Control Transfer Records extension CSRs. > target/riscv: Add support to record CTR entries. > target/riscv: Add CTR sctrclr instruction. > target/riscv: Add support to access ctrsource, ctrtarget, ctrdata > regs. > > target/riscv/cpu.c | 4 + > target/riscv/cpu.h | 14 + > target/riscv/cpu_bits.h | 154 ++++++++++ > target/riscv/cpu_cfg.h | 2 + > target/riscv/cpu_helper.c | 265 +++++++++++++++++ > target/riscv/csr.c | 276 +++++++++++++++++- > target/riscv/helper.h | 9 +- > target/riscv/insn32.decode | 2 +- > .../riscv/insn_trans/trans_privileged.c.inc | 21 +- > target/riscv/insn_trans/trans_rvi.c.inc | 31 ++ > target/riscv/insn_trans/trans_rvzce.c.inc | 20 ++ > target/riscv/op_helper.c | 159 +++++++++- > target/riscv/tcg/tcg-cpu.c | 6 + > target/riscv/translate.c | 10 + > 14 files changed, 960 insertions(+), 13 deletions(-) >