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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-441b2af457bsm12895175e9.24.2025.04.29.23.26.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Apr 2025 23:26:23 -0700 (PDT) Message-ID: Date: Wed, 30 Apr 2025 08:26:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] target/microblaze: Always use TARGET_LONG_BITS == 32 From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, "Edgar E. Iglesias" , Luc Michel , Sai Pavan Boddu , Michal Simek References: <20250212220155.1147144-1-richard.henderson@linaro.org> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 13/2/25 13:37, Philippe Mathieu-Daudé wrote: > +AMD folks > > On 12/2/25 23:01, Richard Henderson wrote: >> Use out-of-line helpers to implement extended address memory ops. >> With this, we can reduce TARGET_LONG_BITS to the more natural 32 >> for this 32-bit cpu. > > I thought about something similar 2 months ago, but then realized > MicroBlaze cores can be synthetized in 64-bit, and IIRC there is > not much missing (I'd say effort would be to add 20% more of what > we currently have). Just wanted to mention before taking the > decision to restrict to 32-bit. OTOH if there are no plan for > adding 64-bit support at AMD, then I'm more than happy to simplify > by considering only 32-bit. I gave this series another go, and figured the microblaze target addition was done way before the 64-bit. C_DATA_SIZE value was fixed as 32, and C_ADDR_SIZE was not mentioned. Later C_DATA_SIZE became configurable as [32, 64] and C_ADDR_SIZE appeared. Indeed what this series does is correctly implement the current target as C_DATA_SIZE=32 (C_ADDR_SIZE=32 implied). I had a quick look at what is missing for C_DATA_SIZE > 32 and it is more than the 20% I first roughly estimated. So with the current implementation, this series is doing the right thing IMHO. Regards, Phil.