From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2 1/2] hw/intc/arm_gicv3: Fix decoding of ID register range
Date: Fri, 24 May 2019 15:13:29 +0200 [thread overview]
Message-ID: <d5c49edf-f864-09ff-be9d-7072cfbb355b@redhat.com> (raw)
In-Reply-To: <20190524124248.28394-2-peter.maydell@linaro.org>
On 5/24/19 2:42 PM, Peter Maydell wrote:
> The GIC ID registers cover an area 0x30 bytes in size
> (12 registers, 4 bytes each). We were incorrectly decoding
> only the first 0x20 bytes.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv3_dist.c | 4 ++--
> hw/intc/arm_gicv3_redist.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c
> index 53c55c57291..e6fe4905fd3 100644
> --- a/hw/intc/arm_gicv3_dist.c
> +++ b/hw/intc/arm_gicv3_dist.c
> @@ -533,7 +533,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
> }
> return MEMTX_OK;
> }
> - case GICD_IDREGS ... GICD_IDREGS + 0x1f:
> + case GICD_IDREGS ... GICD_IDREGS + 0x2f:
> /* ID registers */
> *data = gicv3_idreg(offset - GICD_IDREGS);
> return MEMTX_OK;
> @@ -744,7 +744,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset,
> gicd_write_irouter(s, attrs, irq, r);
> return MEMTX_OK;
> }
> - case GICD_IDREGS ... GICD_IDREGS + 0x1f:
> + case GICD_IDREGS ... GICD_IDREGS + 0x2f:
> case GICD_TYPER:
> case GICD_IIDR:
> /* RO registers, ignore the write */
> diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c
> index 3b0ba6de1ab..8645220d618 100644
> --- a/hw/intc/arm_gicv3_redist.c
> +++ b/hw/intc/arm_gicv3_redist.c
> @@ -233,7 +233,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
> }
> *data = cs->gicr_nsacr;
> return MEMTX_OK;
> - case GICR_IDREGS ... GICR_IDREGS + 0x1f:
> + case GICR_IDREGS ... GICR_IDREGS + 0x2f:
> *data = gicv3_idreg(offset - GICR_IDREGS);
> return MEMTX_OK;
> default:
> @@ -363,7 +363,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
> return MEMTX_OK;
> case GICR_IIDR:
> case GICR_TYPER:
> - case GICR_IDREGS ... GICR_IDREGS + 0x1f:
> + case GICR_IDREGS ... GICR_IDREGS + 0x2f:
> /* RO registers, ignore the write */
> qemu_log_mask(LOG_GUEST_ERROR,
> "%s: invalid guest write to RO register at offset "
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2019-05-24 13:15 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-24 12:42 [Qemu-devel] [PATCH v2 0/2] hw/intc/arm_gicv3: Some simple bugfixes Peter Maydell
2019-05-24 12:42 ` [Qemu-devel] [PATCH v2 1/2] hw/intc/arm_gicv3: Fix decoding of ID register range Peter Maydell
2019-05-24 13:13 ` Philippe Mathieu-Daudé [this message]
2019-05-24 12:42 ` [Qemu-devel] [PATCH v2 2/2] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 Peter Maydell
2019-06-07 13:08 ` Peter Maydell
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