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[83.52.173.228]) by smtp.gmail.com with ESMTPSA id z74sm14412362wmc.2.2019.05.24.06.13.30 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Fri, 24 May 2019 06:13:30 -0700 (PDT) To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20190524124248.28394-1-peter.maydell@linaro.org> <20190524124248.28394-2-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Fri, 24 May 2019 15:13:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190524124248.28394-2-peter.maydell@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.128.67 Subject: Re: [Qemu-devel] [PATCH v2 1/2] hw/intc/arm_gicv3: Fix decoding of ID register range X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/24/19 2:42 PM, Peter Maydell wrote: > The GIC ID registers cover an area 0x30 bytes in size > (12 registers, 4 bytes each). We were incorrectly decoding > only the first 0x20 bytes. > > Signed-off-by: Peter Maydell > --- > hw/intc/arm_gicv3_dist.c | 4 ++-- > hw/intc/arm_gicv3_redist.c | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c > index 53c55c57291..e6fe4905fd3 100644 > --- a/hw/intc/arm_gicv3_dist.c > +++ b/hw/intc/arm_gicv3_dist.c > @@ -533,7 +533,7 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset, > } > return MEMTX_OK; > } > - case GICD_IDREGS ... GICD_IDREGS + 0x1f: > + case GICD_IDREGS ... GICD_IDREGS + 0x2f: > /* ID registers */ > *data = gicv3_idreg(offset - GICD_IDREGS); > return MEMTX_OK; > @@ -744,7 +744,7 @@ static MemTxResult gicd_writel(GICv3State *s, hwaddr offset, > gicd_write_irouter(s, attrs, irq, r); > return MEMTX_OK; > } > - case GICD_IDREGS ... GICD_IDREGS + 0x1f: > + case GICD_IDREGS ... GICD_IDREGS + 0x2f: > case GICD_TYPER: > case GICD_IIDR: > /* RO registers, ignore the write */ > diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c > index 3b0ba6de1ab..8645220d618 100644 > --- a/hw/intc/arm_gicv3_redist.c > +++ b/hw/intc/arm_gicv3_redist.c > @@ -233,7 +233,7 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset, > } > *data = cs->gicr_nsacr; > return MEMTX_OK; > - case GICR_IDREGS ... GICR_IDREGS + 0x1f: > + case GICR_IDREGS ... GICR_IDREGS + 0x2f: > *data = gicv3_idreg(offset - GICR_IDREGS); > return MEMTX_OK; > default: > @@ -363,7 +363,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, > return MEMTX_OK; > case GICR_IIDR: > case GICR_TYPER: > - case GICR_IDREGS ... GICR_IDREGS + 0x1f: > + case GICR_IDREGS ... GICR_IDREGS + 0x2f: > /* RO registers, ignore the write */ > qemu_log_mask(LOG_GUEST_ERROR, > "%s: invalid guest write to RO register at offset " > Reviewed-by: Philippe Mathieu-Daudé