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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Havard Skinnemoen <hskinnemoen@google.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	Richard Henderson <rth@twiddle.net>,
	Eric Blake <eblake@redhat.com>
Cc: "IS20 Avi Fishman" <Avi.Fishman@nuvoton.com>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
	"CS20 KFTing" <kfting@nuvoton.com>,
	qemu-arm <qemu-arm@nongnu.org>, "Cédric Le Goater" <clg@kaod.org>,
	"Cleber Rosa" <crosa@redhat.com>, "Joel Stanley" <joel@jms.id.au>
Subject: Re: [PATCH v7 13/13] tests/acceptance: console boot tests for quanta-gsj
Date: Thu, 20 Aug 2020 07:38:23 +0200	[thread overview]
Message-ID: <d5d11bb5-3f66-5a93-5ea7-1cb01edc8d6a@amsat.org> (raw)
In-Reply-To: <28a30c64-7cc5-4b4f-2be2-b3d3af511cb1@amsat.org>

On 8/20/20 7:29 AM, Philippe Mathieu-Daudé wrote:
> +Eric / Richard for compiler optimizations.
> 
> On 8/20/20 3:53 AM, Havard Skinnemoen wrote:
>> On Tue, Aug 11, 2020 at 8:26 PM Havard Skinnemoen
>> <hskinnemoen@google.com> wrote:
>>>
>>> On Tue, Aug 11, 2020 at 1:48 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>>>> INTERRUPTED: Test interrupted by SIGTERM
>>>> Runner error occurred: Timeout reached
>>>> (240.45 s)
>>>>
>>>> Is that expected?
>>>
>>> I'm not sure why it only happens when running direct kernel boot with
>>> unoptimized qemu, but it seems a little happier if I enable a few more
>>> peripherals that I have queued up (sd, ehci, ohci and rng), though not
>>> enough.
>>>
>>> It still stalls for an awfully long time on "console: Run /init as
>>> init process" though. I'm not sure what it's doing there. With -O2 it
>>> only takes a couple of seconds to move on.
>>
>> So it turns out that the kernel gets _really_ sluggish when skipping
>> the clock initialization normally done by the boot loader.

Hmm IIRC other boards are affected (raspi and orange-pi).

Maybe it is time to define some static inlined boolean function
in "qemu/compiler.h", maybe qemu_build_optimized()? Or not inlined
function but simply expand to true/false:

 /**
  * qemu_build_not_reached()
  *
  * The compiler, during optimization, is expected to prove that a call
  * to this function cannot be reached and remove it.  If the compiler
  * supports QEMU_ERROR, this will be reported at compile time; o therwise
  * this will be reported at link time due to the missing symbol.
  */
 #if defined(__OPTIMIZE__) && !defined(__NO_INLINE__)
 extern void QEMU_NORETURN QEMU_ERROR("code path is reachable")
     qemu_build_not_reached(void);
 #else
 #define qemu_build_not_reached()  g_assert_not_reached()
 #endif
+
+#if defined(__OPTIMIZE__)
+#define qemu_build_optimized() true
+#else
+#define qemu_build_optimized() false
+#endif

>>
>> I changed the reset value of CLKSEL like this:
>>
>> diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
>> index 21ab4200d1..5e9849410f 100644
>> --- a/hw/misc/npcm7xx_clk.c
>> +++ b/hw/misc/npcm7xx_clk.c
>> @@ -67,7 +67,7 @@ enum NPCM7xxCLKRegisters {
>>   */
>>  static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
>>      [NPCM7XX_CLK_CLKEN1]        = 0xffffffff,
>> -    [NPCM7XX_CLK_CLKSEL]        = 0x004aaaaa,
>> +    [NPCM7XX_CLK_CLKSEL]        = 0x004aaba9,
>>      [NPCM7XX_CLK_CLKDIV1]       = 0x5413f855,
>>      [NPCM7XX_CLK_PLLCON0]       = 0x00222101 | PLLCON_LOKI,
>>      [NPCM7XX_CLK_PLLCON1]       = 0x00202101 | PLLCON_LOKI,
>>
>> which switches the CPU core and UART to run from PLL2 instead of
>> CLKREF (25 MHz).
>>
>> With this change, the test passes without optimization:
>>
>>  (02/19) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_quanta_gsj_initrd:
>> PASS (39.62 s)
>>
>> It doesn't look like this change hurts booting from the bootrom (IIUC
>> the nuvoton bootblock overwrites CLKSEL anyway), but it's not super
>> clean.
>>
>> Perhaps I should make it conditional on kernel_filename being set? Or
>> would it be better to provide a write_board_setup hook for this?
> 
> QEMU prefers to avoid ifdef'ry at all cost. However I find this
> approach acceptable (anyway up to the maintainer):
> 
> +static void npcm7xx_clk_cold_reset_fixup(NPCM7xxCLKState *s)
> +{
> +#ifndef __OPTIMIZE__
> +    /*
> +     * When built without optimization, ...
> +     * so run CPU core and UART from PLL2 instead of CLKREF.
> +     */
> +    s->regs[NPCM7XX_CLK_CLKSEL] |= 0x103,
> +#endif
> +}
> 
>  static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
>  {
>      NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
> 
>      QEMU_BUILD_BUG_ON(sizeof(s->regs) != sizeof(cold_reset_values));
> 
>      switch (type) {
>      case RESET_TYPE_COLD:
>          memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
> +        npcm7xx_clk_cold_reset_fixup(s);
>          s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>          return;
>      }
>      ...
> 
> Regards,
> 
> Phil.
> 


  reply	other threads:[~2020-08-20  5:39 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-11  0:45 [PATCH v7 00/13] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-08-11  0:45 ` [PATCH v7 01/13] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
2020-08-11  0:45 ` [PATCH v7 02/13] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
2020-08-12 10:31   ` Philippe Mathieu-Daudé
2020-08-11  0:45 ` [PATCH v7 03/13] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
2020-08-11  0:45 ` [PATCH v7 04/13] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
2020-08-11  0:45 ` [PATCH v7 05/13] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 06/13] roms: Add virtual Boot ROM for NPCM7xx SoCs Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 07/13] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
2020-08-11  8:38   ` Philippe Mathieu-Daudé
2020-08-11  0:46 ` [PATCH v7 08/13] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 09/13] hw/mem: Stubbed out NPCM7xx Memory Controller model Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 10/13] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 11/13] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 12/13] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
2020-08-11  0:46 ` [PATCH v7 13/13] tests/acceptance: console boot tests for quanta-gsj Havard Skinnemoen
2020-08-11  8:48   ` Philippe Mathieu-Daudé
2020-08-12  3:26     ` Havard Skinnemoen
2020-08-20  1:53       ` Havard Skinnemoen
2020-08-20  5:29         ` Philippe Mathieu-Daudé
2020-08-20  5:38           ` Philippe Mathieu-Daudé [this message]
2020-08-20 16:24           ` Havard Skinnemoen
2020-08-20 17:46             ` Philippe Mathieu-Daudé
2020-08-20 20:30               ` Havard Skinnemoen
2020-08-22 21:40                 ` Philippe Mathieu-Daudé

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