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Mon, 4 Sep 2023 14:30:34 +0000 (GMT) Message-ID: Subject: Re: [risu PATCH 0/4] Add support for s390x to RISU From: Ilya Leoshkevich To: Thomas Huth , Peter Maydell Cc: qemu-s390x@nongnu.org, qemu-devel@nongnu.org, Richard Henderson , David Hildenbrand Date: Mon, 04 Sep 2023 16:30:34 +0200 In-Reply-To: <20230904140040.33153-1-thuth@redhat.com> References: <20230904140040.33153-1-thuth@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 (3.48.4-1.fc38) MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: _yaC11pbCieQ4lD_2dbp3VPe6ogbdaOA X-Proofpoint-ORIG-GUID: XpGxPd-2068u2wi52LJGL3fTGnYMRNFk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-04_07,2023-08-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 clxscore=1015 adultscore=0 suspectscore=0 bulkscore=0 malwarescore=0 mlxlogscore=742 impostorscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309040126 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 2023-09-04 at 16:00 +0200, Thomas Huth wrote: > =C2=A0Hi Peter! >=20 > Here are some patches that add basic support for s390x to RISU. > It's still quite limited, e.g. no support for load/store memory > operations yet, but the basics with simple 16-bit or 32-bit > instructions work already fine. >=20 > (In the long run, we'd need to support instructions with 48-bit > length on s390x, too, since most newer "interesting" instructions > like e.g. vector SIMD instructions are encoded with 48 bit. This > will require modifications to the generic code, too, so I limited > my initial implementation to 16-bit and 32-bit instruction length > support to keep the code self-contained in the s390x architecture > specific files) What's also interesting about SIMD, is that floating-point instructions clobber the upper parts of vector registers. I wonder if there is a way to systematically solve this? In my scripts the solution isn't pretty: insn =3D gdb.execute("x/i $pc", to_string=3DTrue) print(insn) gdb.execute("stepi") if "%f" in insn: [ Skip comparison ] I think there are also a few cases in non-SIMD areas, where PoP basically says "if conditions X and Y hold, the output is unpredictable". One other thing - for not-so-near future - is it possible to integrate this with coverage-based fuzzers? I.e., somehow generate the instructions based on the coverage signal. Maybe even make sure that the signal comes from JITed code too. I wanted to try AFLplusplus in QEMU mode for this purpose (which would ultimately run QEMU in QEMU), but never found the time. [...]