Re: [Qemu-devel] [PATCH 05/26] target/arm: Honour M-profile FP enable bits

[Richard Henderson <richard.henderson@linaro.org>]

On 4/16/19 5:57 AM, Peter Maydell wrote:
> Like AArch64, M-profile floating point has no FPEXC enable
> bit to gate floating point; so always set the VFPEN TB flag.
> 
> M-profile also has CPACR and NSACR similar to A-profile;
> they behave slightly differently:
>  * the CPACR is banked between Secure and Non-Secure
>  * if the NSACR forces a trap then this is taken to
>    the Secure state, not the Non-Secure state
> 
> Honour the CPACR and NSACR settings. The NSACR handling
> requires us to borrow the exception.target_el field
> (usually meaningless for M profile) to distinguish the
> NOCP UsageFault taken to Secure state from the more
> usual fault taken to the current security state.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/helper.c    | 55 +++++++++++++++++++++++++++++++++++++++---
>  target/arm/translate.c | 10 ++++++--
>  2 files changed, 60 insertions(+), 5 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~