[Qemu-devel] [PATCH for-2.11 0/4] ppc64: add e6500

[Qemu-devel] [PATCH for-2.11 0/4] ppc64: add e6500

[KONRAD Frederic]

Hi,

Those are some patches to add basic e6500 support for the moment e5500 with a
correct MMU configuration and supported instructions.
Some (maybe a lot of) things are missing (ie: the thread support) but it is
enough to boot a propietary OS on my side.

The first two patches are fixes when using MAV 2.0 MMU.
The two last patches introduces the e6500.

This can be cloned here:
https://github.com/FredKonrad/qemu.git branch e6500

Thanks,
Fred

KONRAD Frederic (4):
  booke206: fix booke206_tlbnps for mav 2.0
  booke206: fix tlbnps for fixed size TLB
  booke206: allow to specify an mmucfg value at the init
  ppc64: introduce e6500

 target/ppc/cpu-models.c     |   2 +
 target/ppc/cpu-models.h     |   1 +
 target/ppc/cpu.h            |  26 +++++++++++-
 target/ppc/mmu_helper.c     |  16 ++++---
 target/ppc/translate_init.c | 100 +++++++++++++++++++++++++++++++++++++++++---
 5 files changed, 132 insertions(+), 13 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH for-2.11 1/4] booke206: fix booke206_tlbnps for mav 2.0

[KONRAD Frederic]

This fixes booke206_tlbnps for MAV 2.0 by checking the MMUCFG register and
return directly the right tlbnps instead of computing it from non existing
field.

Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
 target/ppc/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6ee2a26..d2faea9 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2472,10 +2472,10 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
 /* returns bitmap of supported page sizes for a given TLB */
 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
 {
-    bool mav2 = false;
     uint32_t ret = 0;
 
-    if (mav2) {
+    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+        /* MAV2 */
         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
     } else {
         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
-- 
1.8.3.1

[Qemu-devel] [PATCH for-2.11 2/4] booke206: fix tlbnps for fixed size TLB

[KONRAD Frederic]

Some OS don't populate the TSIZE field when using a fixed size TLB which result
in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be
ignored.

Fix this wrong behavior with MAV 2.0.

Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
 target/ppc/cpu.h        | 22 ++++++++++++++++++++++
 target/ppc/mmu_helper.c | 16 ++++++++++------
 2 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d2faea9..32a44a8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2490,6 +2490,28 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
     return ret;
 }
 
+static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
+                                            ppcmas_tlb_t *tlb)
+{
+    uint8_t i;
+    int32_t tsize = -1;
+
+    for (i = 0; i < 32; i++) {
+        if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
+            if (tsize == -1) {
+                tsize = i;
+            } else {
+                return;
+            }
+        }
+    }
+
+    /* TLBnPS unimplemented? Odd.. */
+    assert(tsize != -1);
+    tlb->mas1 &= ~MAS1_TSIZE_MASK;
+    tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
+}
+
 #endif
 
 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f06b938..2a1f990 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2632,12 +2632,16 @@ void helper_booke206_tlbwe(CPUPPCState *env)
         env->spr[SPR_BOOKE_MAS3];
     tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
 
-    /* MAV 1.0 only */
-    if (!(tlbncfg & TLBnCFG_AVAIL)) {
-        /* force !AVAIL TLB entries to correct page size */
-        tlb->mas1 &= ~MAS1_TSIZE_MASK;
-        /* XXX can be configured in MMUCSR0 */
-        tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+    if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+        /* For TLB which has a fixed size TSIZE is ignored with MAV2 */
+        booke206_fixed_size_tlbn(env, tlbn, tlb);
+    } else {
+        if (!(tlbncfg & TLBnCFG_AVAIL)) {
+            /* force !AVAIL TLB entries to correct page size */
+            tlb->mas1 &= ~MAS1_TSIZE_MASK;
+            /* XXX can be configured in MMUCSR0 */
+            tlb->mas1 |= (tlbncfg & TLBnCFG_MINSIZE) >> 12;
+        }
     }
 
     /* Make a mask from TLB size to discard invalid bits in EPN field */
-- 
1.8.3.1

[Qemu-devel] [PATCH for-2.11 3/4] booke206: allow to specify an mmucfg value at the init

[KONRAD Frederic]

This allows to init the MMUCFG SPR with a non NULL value.

Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
 target/ppc/translate_init.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 01723bd..2627cbe 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -1842,7 +1842,7 @@ static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
 
 /* BookE 2.06 storage control registers */
 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
-                              uint32_t *tlbncfg)
+                             uint32_t *tlbncfg, uint32_t mmucfg)
 {
 #if !defined(CONFIG_USER_ONLY)
     const char *mas_names[8] = {
@@ -1886,7 +1886,7 @@ static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
     spr_register(env, SPR_MMUCFG, "MMUCFG",
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, SPR_NOACCESS,
-                 0x00000000); /* TOFIX */
+                 mmucfg);
     switch (env->nb_ways) {
     case 4:
         spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
@@ -4615,7 +4615,7 @@ static void init_proc_e200(CPUPPCState *env)
                  &spr_read_spefscr, &spr_write_spefscr,
                  0x00000000);
     /* Memory management */
-    gen_spr_BookE206(env, 0x0000005D, NULL);
+    gen_spr_BookE206(env, 0x0000005D, NULL, 0);
     /* XXX : not implemented */
     spr_register(env, SPR_HID0, "HID0",
                  SPR_NOACCESS, SPR_NOACCESS,
@@ -4900,6 +4900,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
                     | 0x0020; /* 32 kb */
     uint32_t l1cfg1 = 0x3800  /* 8 ways */
                     | 0x0020; /* 32 kb */
+    uint32_t mmucfg = 0;
 #if !defined(CONFIG_USER_ONLY)
     int i;
 #endif
@@ -4974,7 +4975,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
     default:
         cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
     }
-    gen_spr_BookE206(env, 0x000000DF, tlbncfg);
+    gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg);
     /* XXX : not implemented */
     spr_register(env, SPR_HID0, "HID0",
                  SPR_NOACCESS, SPR_NOACCESS,
-- 
1.8.3.1

[Qemu-devel] [PATCH for-2.11 4/4] ppc64: introduce e6500

[KONRAD Frederic]

This introduces e6500 core.

Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
 target/ppc/cpu-models.c     |  2 +
 target/ppc/cpu-models.h     |  1 +
 target/ppc/translate_init.c | 91 ++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index 4d3e635..e0d9faf 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -693,6 +693,8 @@
 #ifdef TARGET_PPC64
     POWERPC_DEF_SVR("e5500", "e5500",
                     CPU_POWERPC_e5500,        POWERPC_SVR_E500,      e5500)
+    POWERPC_DEF_SVR("e6500", "e6500",
+                    CPU_POWERPC_e6500,        POWERPC_SVR_E500,      e6500)
 #endif
     /* PowerPC e500 microcontrollers                                         */
     POWERPC_DEF_SVR("MPC8533_v10", "MPC8533 v1.0",
diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h
index b563c45..eaa6849 100644
--- a/target/ppc/cpu-models.h
+++ b/target/ppc/cpu-models.h
@@ -346,6 +346,7 @@ enum {
     CPU_POWERPC_e500v2_v30         = 0x80210030,
     CPU_POWERPC_e500mc             = 0x80230020,
     CPU_POWERPC_e5500              = 0x80240020,
+    CPU_POWERPC_e6500              = 0x80400020,
     /* MPC85xx microcontrollers */
 #define CPU_POWERPC_MPC8533_v10      CPU_POWERPC_e500v2_v21
 #define CPU_POWERPC_MPC8533_v11      CPU_POWERPC_e500v2_v22
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 2627cbe..9d2b050 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -4888,6 +4888,7 @@ enum fsl_e500_version {
     fsl_e500v2,
     fsl_e500mc,
     fsl_e5500,
+    fsl_e6500,
 };
 
 static void init_proc_e500(CPUPPCState *env, int version)
@@ -4922,6 +4923,9 @@ static void init_proc_e500(CPUPPCState *env, int version)
         case fsl_e5500:
             ivor_mask = 0x000003FE0000FFFFULL;
             break;
+        case fsl_e6500:
+            ivor_mask = 0x000003FF0000FFFFULL;
+            break;
     }
     gen_spr_BookE(env, ivor_mask);
     gen_spr_usprg3(env);
@@ -4954,6 +4958,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
         tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
         tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
         break;
+    case fsl_e6500:
+        mmucfg = 0x6510B45;
+        env->nb_pids = 1;
+        tlbncfg[0] = 0x08052400;
+        tlbncfg[1] = 0x40028040;
+        break;
     default:
         cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
     }
@@ -4972,6 +4982,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
         l1cfg0 |= 0x1000000; /* 64 byte cache block size */
         l1cfg1 |= 0x1000000; /* 64 byte cache block size */
         break;
+    case fsl_e6500:
+        env->dcache_line_size = 32;
+        env->icache_line_size = 32;
+        l1cfg0 |= 0x0F83820;
+        l1cfg1 |= 0x0B83820;
+        break;
     default:
         cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
     }
@@ -5050,7 +5066,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
                  &spr_read_generic, SPR_NOACCESS,
                  0x00000000);
     /* XXX better abstract into Emb.xxx features */
-    if (version == fsl_e5500) {
+    if ((version == fsl_e5500) || (version == fsl_e6500)) {
         spr_register(env, SPR_BOOKE_EPCR, "EPCR",
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
@@ -5062,6 +5078,30 @@ static void init_proc_e500(CPUPPCState *env, int version)
         ivpr_mask = (target_ulong)~0xFFFFULL;
     }
 
+    if (version == fsl_e6500) {
+        spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     0x00000000);
+        spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     0x00000000);
+        /* Thread identification */
+        spr_register(env, SPR_TIR, "TIR",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     0x00000000);
+        spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     0x00000004);
+        spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, SPR_NOACCESS,
+                     0x7FFFFFFC);
+    }
+
 #if !defined(CONFIG_USER_ONLY)
     env->nb_tlb = 0;
     env->tlb_type = TLB_MAS;
@@ -5254,6 +5294,55 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
     pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
                  POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
 }
+
+static void init_proc_e6500(CPUPPCState *env)
+{
+    init_proc_e500(env, fsl_e6500);
+}
+
+POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+    dc->desc = "e6500 core";
+    pcc->init_proc = init_proc_e6500;
+    pcc->check_pow = check_pow_none;
+    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
+                       PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
+                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
+                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
+                       PPC_FLOAT | PPC_FLOAT_FRES |
+                       PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
+                       PPC_FLOAT_STFIWX | PPC_WAIT |
+                       PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
+                       PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
+    pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | \
+                        PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
+    pcc->msr_mask = (1ull << MSR_CM) |
+                    (1ull << MSR_GS) |
+                    (1ull << MSR_UCLE) |
+                    (1ull << MSR_CE) |
+                    (1ull << MSR_EE) |
+                    (1ull << MSR_PR) |
+                    (1ull << MSR_FP) |
+                    (1ull << MSR_ME) |
+                    (1ull << MSR_FE0) |
+                    (1ull << MSR_DE) |
+                    (1ull << MSR_FE1) |
+                    (1ull << MSR_IS) |
+                    (1ull << MSR_DS) |
+                    (1ull << MSR_PX) |
+                    (1ull << MSR_RI) |
+                    (1ull << MSR_VR);
+    pcc->mmu_model = POWERPC_MMU_BOOKE206;
+    pcc->excp_model = POWERPC_EXCP_BOOKE;
+    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
+    pcc->bfd_mach = bfd_mach_ppc_e500;
+    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
+                 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
+}
+
 #endif
 
 /* Non-embedded PowerPC                                                      */
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH for-2.11 0/4] ppc64: add e6500

[David Gibson]

[-- Attachment #1: Type: text/plain, Size: 1468 bytes --]

On Mon, Aug 07, 2017 at 05:50:44PM +0200, KONRAD Frederic wrote:
> Hi,
> 
> Those are some patches to add basic e6500 support for the moment e5500 with a
> correct MMU configuration and supported instructions.
> Some (maybe a lot of) things are missing (ie: the thread support) but it is
> enough to boot a propietary OS on my side.
> 
> The first two patches are fixes when using MAV 2.0 MMU.
> The two last patches introduces the e6500.
> 
> This can be cloned here:
> https://github.com/FredKonrad/qemu.git branch e6500

Looks sane as best as my minimal knowledge of e500 goes.  Applied to
ppc-for-2.11.  Alex, if you (or anyone with knowledge of this
platform) has objections, I'll reconsider.

> 
> Thanks,
> Fred
> 
> KONRAD Frederic (4):
>   booke206: fix booke206_tlbnps for mav 2.0
>   booke206: fix tlbnps for fixed size TLB
>   booke206: allow to specify an mmucfg value at the init
>   ppc64: introduce e6500
> 
>  target/ppc/cpu-models.c     |   2 +
>  target/ppc/cpu-models.h     |   1 +
>  target/ppc/cpu.h            |  26 +++++++++++-
>  target/ppc/mmu_helper.c     |  16 ++++---
>  target/ppc/translate_init.c | 100 +++++++++++++++++++++++++++++++++++++++++---
>  5 files changed, 132 insertions(+), 13 deletions(-)
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
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Re: [Qemu-devel] [PATCH for-2.11 0/4] ppc64: add e6500

[Alexander Graf]

On 09.08.17 08:13, David Gibson wrote:
> On Mon, Aug 07, 2017 at 05:50:44PM +0200, KONRAD Frederic wrote:
>> Hi,
>>
>> Those are some patches to add basic e6500 support for the moment e5500 with a
>> correct MMU configuration and supported instructions.
>> Some (maybe a lot of) things are missing (ie: the thread support) but it is
>> enough to boot a propietary OS on my side.
>>
>> The first two patches are fixes when using MAV 2.0 MMU.
>> The two last patches introduces the e6500.
>>
>> This can be cloned here:
>> https://github.com/FredKonrad/qemu.git branch e6500
> 
> Looks sane as best as my minimal knowledge of e500 goes.  Applied to
> ppc-for-2.11.  Alex, if you (or anyone with knowledge of this
> platform) has objections, I'll reconsider.

I think it's good enough. We're missing a *lot* of e6500 features, but 
if this is useful to Frederic, I don't see a good reason to hold it back.

Alex