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From: Richard Henderson <richard.henderson@linaro.org>
To: Aaron Lindsay <aaron@os.amperecomputing.com>,
	"qemu-arm@nongnu.org" <qemu-arm@nongnu.org>,
	Peter Maydell <peter.maydell@linaro.org>,
	Alistair Francis <alistair.francis@xilinx.com>,
	Wei Huang <wei@redhat.com>,
	Peter Crosthwaite <crosthwaite.peter@gmail.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
	Michael Spradling <mspradli@codeaurora.org>,
	Digant Desai <digantd@codeaurora.org>,
	Aaron Lindsay <alindsay@codeaurora.org>,
	SM-Aaron Lindsay <alindsay@os.amperecomputing.com>
Subject: Re: [Qemu-devel] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow
Date: Fri, 30 Nov 2018 09:13:01 -0800	[thread overview]
Message-ID: <d6fde9c7-b72e-ae9d-817b-71c3d6369dbc@linaro.org> (raw)
In-Reply-To: <20181120212553.8480-14-aaron@os.amperecomputing.com>

On 11/20/18 1:26 PM, Aaron Lindsay wrote:
> Setup a QEMUTimer to get a callback when we expect counters to next
> overflow and trigger an interrupt at that time.
> 
> Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
> Signed-off-by: Aaron Lindsay <alindsay@os.amperecomputing.com>
> ---
>  target/arm/cpu.c    |  12 +++++
>  target/arm/cpu.h    |   7 +++
>  target/arm/helper.c | 126 +++++++++++++++++++++++++++++++++++++++++---
>  3 files changed, 139 insertions(+), 6 deletions(-)
> 
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 208a08e867..7311a48e3c 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -827,6 +827,13 @@ static void arm_cpu_finalizefn(Object *obj)
>          QLIST_REMOVE(hook, node);
>          g_free(hook);
>      }
> +#ifndef CONFIG_USER_ONLY
> +    if (arm_feature(&cpu->env, ARM_FEATURE_PMU) && cpu->pmu_timer) {

No need for two tests here.  Just check cpu->pmu_timer.
(If it's set for any reason it should be freed, surely.)

> @@ -1305,7 +1338,18 @@ void pmccntr_op_start(CPUARMState *env)
>              eff_cycles /= 64;
>          }
>  
> -        env->cp15.c15_ccnt = eff_cycles - env->cp15.c15_ccnt_delta;
> +        uint64_t new_pmccntr = eff_cycles - env->cp15.c15_ccnt_delta;
> +
> +        unsigned int overflow_bit = (env->cp15.c9_pmcr & PMCRLC) ? 63 : 31;
> +        uint64_t overflow_mask = (uint64_t)1 << overflow_bit;
> +        if (!(new_pmccntr & overflow_mask) &&
> +                (env->cp15.c15_ccnt & overflow_mask)) {

Fyi, this expression is

    env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask

> +            env->cp15.c9_pmovsr |= (1 << 31);
> +            new_pmccntr &= ~overflow_mask;

Why this line?  You just checked that overflow_mask was unset in new_pmccntr above.

> @@ -1318,13 +1362,28 @@ void pmccntr_op_start(CPUARMState *env)
>  void pmccntr_op_finish(CPUARMState *env)
>  {
>      if (pmu_counter_enabled(env, 31)) {
> -        uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
> +#ifndef CONFIG_USER_ONLY
> +        uint64_t delta;
> +        if (env->cp15.c9_pmcr & PMCRLC) {
> +            delta = UINT64_MAX - env->cp15.c15_ccnt + 1;
> +        } else {
> +            delta = UINT32_MAX - (uint32_t)env->cp15.c15_ccnt + 1;
> +        }

FWIW, this is the same as

    delta = -env->cp15.c15_ccnt;
    if (!(env->cp15.c9_pmcr & PMCRLC)) {
        delta = (uint32_t)delta;
    }


r~

  reply	other threads:[~2018-11-30 17:15 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-20 21:26 [Qemu-devel] [PATCH v8 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 01/13] migration: Add post_save function to VMStateDescription Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 02/13] target/arm: Reorganize PMCCNTR accesses Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 03/13] target/arm: Swap PMU values before/after migrations Aaron Lindsay
2018-11-30 16:07   ` Peter Maydell
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 04/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 05/13] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 06/13] target/arm: Implement PMOVSSET Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 07/13] target-arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] Aaron Lindsay
2018-11-30 16:10   ` Peter Maydell
2018-12-03 20:44     ` Aaron Lindsay
2018-12-03 22:19       ` Peter Maydell
2018-12-03 22:57         ` Richard Henderson
2018-12-05 13:00           ` Aaron Lindsay
2018-12-05 15:00             ` Peter Maydell
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 08/13] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 Aaron Lindsay
2018-11-30 16:14   ` Peter Maydell
2018-12-03 20:30     ` Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 09/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 10/13] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 11/13] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 12/13] target/arm: Implement PMSWINC Aaron Lindsay
2018-11-20 21:26 ` [Qemu-devel] [PATCH v8 13/13] target/arm: Send interrupts on PMU counter overflow Aaron Lindsay
2018-11-30 17:13   ` Richard Henderson [this message]
2018-11-30 17:56     ` Aaron Lindsay
2018-11-30 18:19       ` Richard Henderson
2018-11-30 19:57         ` Aaron Lindsay
2018-11-30 20:43           ` Richard Henderson

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