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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 5/5] target/arm: Correctly implement Feat_DoubleLock Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220630194116.3438513-1-peter.maydell@linaro.org> <20220630194116.3438513-6-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220630194116.3438513-6-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/1/22 01:11, Peter Maydell wrote: > +static inline bool isar_feature_any_doublelock(const ARMISARegisters *id) > +{ > + /* > + * We can't just OR together the aa32 and aa64 checks, because > + * if there is no AArch64 support the aa64 function will default > + * to returning true for a zero id_aa64dfr0. > + * We use "is id_aa64pfr0 non-zero" as a proxy for "do we have > + * the AArch64 ID register values in id", because it's always the > + * case that ID_AA64PFR0_EL1.EL0 at least will be non-zero. > + */ > + if (id->id_aa64pfr0) { > + return isar_feature_aa64_doublelock(id); > + } > + return isar_feature_aa32_doublelock(id); > +} If you're going to rely on this, you need to clear this register for -cpu aarch64=off. It's probably easier to drop this function... > +static void osdlr_write(CPUARMState *env, const ARMCPRegInfo *ri, > + uint64_t value) > +{ > + /* > + * Only defined bit is bit 0 (DLK); if Feat_DoubleLock is not > + * implemented this is RAZ/WI. > + */ > + if (cpu_isar_feature(any_doublelock, env_archcpu(env))) { ... and use if (arm_feature(env, ARM_FEATURE_AARCH64) ? cpu_isar_feature(aa64_doublelock, cpu) : cpu_isar_feature(aa32_doublelock, cpu)) { since it's just used once. r~