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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7c56453475esm216461985a.22.2025.03.12.08.15.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 08:15:14 -0700 (PDT) Message-ID: Date: Wed, 12 Mar 2025 16:15:10 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 03/20] hw/arm/smmuv3-accel: Add initial infrastructure for smmuv3-accel device Content-Language: en-US To: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, jgg@nvidia.com, nicolinc@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, linuxarm@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-4-shameerali.kolothum.thodi@huawei.com> From: Eric Auger In-Reply-To: <20250311141045.66620-4-shameerali.kolothum.thodi@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Shameer, On 3/11/25 3:10 PM, Shameer Kolothum wrote: > Based on SMMUv3 as a parent device, add a user-creatable smmuv3-accel > device. In order to support vfio-pci dev assignment with a Guest guest > SMMUv3, the physical SMMUv3 has to be configured in nested(S1+s2) nested (s1+s2) > mode, with Guest owning the S1 page tables. Subsequent patches will the guest > add support for smmuv3-accel to provide this. Can't this -accel smmu also works with emulated devices? Do we want an exclusive usage? I would also document in the commit msg that a new property is added in the parent SMMU (accel). Will this device be migratable? Do we need a migration blocker? > > Signed-off-by: Shameer Kolothum > --- > hw/arm/Kconfig | 5 ++++ > hw/arm/meson.build | 1 + > hw/arm/smmu-common.c | 1 + > hw/arm/smmuv3-accel.c | 51 +++++++++++++++++++++++++++++++++++ > include/hw/arm/smmu-common.h | 3 +++ > include/hw/arm/smmuv3-accel.h | 31 +++++++++++++++++++++ > 6 files changed, 92 insertions(+) > create mode 100644 hw/arm/smmuv3-accel.c > create mode 100644 include/hw/arm/smmuv3-accel.h > > diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig > index 504841ccab..f889842dd8 100644 > --- a/hw/arm/Kconfig > +++ b/hw/arm/Kconfig > @@ -14,6 +14,7 @@ config ARM_VIRT > select ARM_GIC > select ACPI > select ARM_SMMUV3 > + select ARM_SMMUV3_ACCEL > select GPIO_KEY > select DEVICE_TREE > select FW_CFG_DMA > @@ -596,6 +597,10 @@ config FSL_IMX7 > config ARM_SMMUV3 > bool > > +config ARM_SMMUV3_ACCEL > + select ARM_SMMUV3 > + bool > + > config FSL_IMX6UL > bool > default y > diff --git a/hw/arm/meson.build b/hw/arm/meson.build > index 465c757f97..e8593363b0 100644 > --- a/hw/arm/meson.build > +++ b/hw/arm/meson.build > @@ -55,6 +55,7 @@ arm_ss.add(when: 'CONFIG_MUSCA', if_true: files('musca.c')) > arm_ss.add(when: 'CONFIG_ARMSSE', if_true: files('armsse.c')) > arm_ss.add(when: 'CONFIG_FSL_IMX7', if_true: files('fsl-imx7.c', 'mcimx7d-sabre.c')) > arm_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmuv3.c')) > +arm_ss.add(when: 'CONFIG_ARM_SMMUV3_ACCEL', if_true: files('smmuv3-accel.c')) > arm_ss.add(when: 'CONFIG_FSL_IMX6UL', if_true: files('fsl-imx6ul.c', 'mcimx6ul-evk.c')) > arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) > arm_ss.add(when: 'CONFIG_XEN', if_true: files( > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > index 8c1b407b82..f5caf1665c 100644 > --- a/hw/arm/smmu-common.c > +++ b/hw/arm/smmu-common.c > @@ -943,6 +943,7 @@ static const Property smmu_dev_properties[] = { > DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), > DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, > TYPE_PCI_BUS, PCIBus *), > + DEFINE_PROP_BOOL("accel", SMMUState, accel, false), > }; > > static void smmu_base_class_init(ObjectClass *klass, void *data) > diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c > new file mode 100644 > index 0000000000..c327661636 > --- /dev/null > +++ b/hw/arm/smmuv3-accel.c > @@ -0,0 +1,51 @@ > +/* > + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd > + * Copyright (C) 2025 NVIDIA > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include "qemu/osdep.h" > + > +#include "hw/arm/smmuv3-accel.h" > + > +static void smmu_accel_realize(DeviceState *d, Error **errp) > +{ > + SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(d); > + SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_GET_CLASS(s_accel); > + SysBusDevice *dev = SYS_BUS_DEVICE(d); > + Error *local_err = NULL; > + > + object_property_set_bool(OBJECT(dev), "accel", true, &error_abort); you shouldn't need dev and simply use OBJECT(d) > + c->parent_realize(d, &local_err); > + if (local_err) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > +static void smmuv3_accel_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + SMMUv3AccelClass *c = ARM_SMMUV3_ACCEL_CLASS(klass); > + > + device_class_set_parent_realize(dc, smmu_accel_realize, > + &c->parent_realize); > + dc->hotpluggable = false; > +} > + > +static const TypeInfo smmuv3_accel_type_info = { > + .name = TYPE_ARM_SMMUV3_ACCEL, > + .parent = TYPE_ARM_SMMUV3, > + .instance_size = sizeof(SMMUv3AccelState), > + .class_size = sizeof(SMMUv3AccelClass), > + .class_init = smmuv3_accel_class_init, > +}; > + > +static void smmuv3_accel_register_types(void) > +{ > + type_register_static(&smmuv3_accel_type_info); > +} > + > +type_init(smmuv3_accel_register_types) > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index d1a4a64551..b5c63cfd5d 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -157,6 +157,9 @@ struct SMMUState { > QLIST_HEAD(, SMMUDevice) devices_with_notifiers; > uint8_t bus_num; > PCIBus *primary_bus; > + > + /* For smmuv3-accel */ > + bool accel; > }; > > struct SMMUBaseClass { > diff --git a/include/hw/arm/smmuv3-accel.h b/include/hw/arm/smmuv3-accel.h > new file mode 100644 > index 0000000000..56fe376bf4 > --- /dev/null > +++ b/include/hw/arm/smmuv3-accel.h > @@ -0,0 +1,31 @@ > +/* > + * Copyright (c) 2025 Huawei Technologies R & D (UK) Ltd > + * Copyright (C) 2025 NVIDIA > + * Written by Nicolin Chen, Shameer Kolothum > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_ARM_SMMUV3_ACCEL_H > +#define HW_ARM_SMMUV3_ACCEL_H > + > +#include "hw/arm/smmu-common.h" > +#include "hw/arm/smmuv3.h" > +#include "qom/object.h" > + > +#define TYPE_ARM_SMMUV3_ACCEL "arm-smmuv3-accel" > +OBJECT_DECLARE_TYPE(SMMUv3AccelState, SMMUv3AccelClass, ARM_SMMUV3_ACCEL) > + > +struct SMMUv3AccelState { > + SMMUv3State smmuv3_state; > +}; > + > +struct SMMUv3AccelClass { > + /*< private >*/ > + SMMUv3Class smmuv3_class; > + /*< public >*/ > + > + DeviceRealize parent_realize; > +}; > + > +#endif /* HW_ARM_SMMUV3_ACCEL_H */ Thanks Eric