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Tue, 13 Jul 2021 00:46:06 -0700 (PDT) Received: from [10.0.20.43] ([103.217.166.124]) by smtp.googlemail.com with ESMTPSA id u19sm12787278pfi.4.2021.07.13.00.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 00:46:06 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 2/3] hw: aspeed_gpio: Simplify 1.8V defines From: Rashmica Gupta To: Joel Stanley , =?ISO-8859-1?Q?C=E9dric?= Le Goater Date: Tue, 13 Jul 2021 17:46:02 +1000 In-Reply-To: <20210713065854.134634-3-joel@jms.id.au> References: <20210713065854.134634-1-joel@jms.id.au> <20210713065854.134634-3-joel@jms.id.au> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.38.4 (3.38.4-1.fc33) MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=rashmica.g@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, 2021-07-13 at 16:28 +0930, Joel Stanley wrote: > There's no need to define the registers relative to the 0x800 offset > where the controller is mapped, as the device is instantiated as it's > own model at the correct memory address. > > Simplify the defines and remove the offset to save future confusion. > > Signed-off-by: Joel Stanley Makes sense, and it is cleaner. Reviewed-by: Rashmica Gupta > --- >  hw/gpio/aspeed_gpio.c | 73 +++++++++++++++++++++-------------------- > -- >  1 file changed, 36 insertions(+), 37 deletions(-) > > diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c > index b3dec4448009..dc721aec5da7 100644 > --- a/hw/gpio/aspeed_gpio.c > +++ b/hw/gpio/aspeed_gpio.c > @@ -169,44 +169,43 @@ >   >  /* AST2600 only - 1.8V gpios */ >  /* > - * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets > 0x0-0x198) > - * and additional 1.8V gpios (memory offsets 0x800-0x9D4). > + * The AST2600 two copies of the GPIO controller: the same 3.6V > gpios as the > + * AST2400 (memory offsets 0x0-0x198) and a second controller with > 1.8V gpios > + * (memory offsets 0x800-0x9D4). >   */ > -#define GPIO_1_8V_REG_OFFSET          0x800 > -#define GPIO_1_8V_ABCD_DATA_VALUE     ((0x800 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_DIRECTION      ((0x804 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INT_ENABLE     ((0x808 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INT_SENS_0     ((0x80C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INT_SENS_1     ((0x810 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INT_SENS_2     ((0x814 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INT_STATUS     ((0x818 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_DATA_VALUE        ((0x820 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_DIRECTION         ((0x824 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INT_ENABLE        ((0x828 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INT_SENS_0        ((0x82C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INT_SENS_1        ((0x830 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INT_SENS_2        ((0x834 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INT_STATUS        ((0x838 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_RESET_TOLERANT    ((0x83C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_DEBOUNCE_1     ((0x840 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_DEBOUNCE_2     ((0x844 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_DEBOUNCE_1        ((0x848 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_DEBOUNCE_2        ((0x84C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_DEBOUNCE_TIME_1     ((0x850 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_DEBOUNCE_TIME_2     ((0x854 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_DEBOUNCE_TIME_3     ((0x858 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_COMMAND_SRC_0  ((0x860 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_COMMAND_SRC_1  ((0x864 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_COMMAND_SRC_0     ((0x868 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_COMMAND_SRC_1     ((0x86C - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_DATA_READ      ((0x8C0 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_DATA_READ         ((0x8C4 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_ABCD_INPUT_MASK     ((0x9D0 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_E_INPUT_MASK        ((0x9D4 - > GPIO_1_8V_REG_OFFSET) >> 2) > -#define GPIO_1_8V_MEM_SIZE            0x9D8 > -#define GPIO_1_8V_REG_ARRAY_SIZE      ((GPIO_1_8V_MEM_SIZE - \ > -                                      GPIO_1_8V_REG_OFFSET) >> 2) > +#define GPIO_1_8V_ABCD_DATA_VALUE     (0x000 >> 2) > +#define GPIO_1_8V_ABCD_DIRECTION      (0x004 >> 2) > +#define GPIO_1_8V_ABCD_INT_ENABLE     (0x008 >> 2) > +#define GPIO_1_8V_ABCD_INT_SENS_0     (0x00C >> 2) > +#define GPIO_1_8V_ABCD_INT_SENS_1     (0x010 >> 2) > +#define GPIO_1_8V_ABCD_INT_SENS_2     (0x014 >> 2) > +#define GPIO_1_8V_ABCD_INT_STATUS     (0x018 >> 2) > +#define GPIO_1_8V_ABCD_RESET_TOLERANT (0x01C >> 2) > +#define GPIO_1_8V_E_DATA_VALUE        (0x020 >> 2) > +#define GPIO_1_8V_E_DIRECTION         (0x024 >> 2) > +#define GPIO_1_8V_E_INT_ENABLE        (0x028 >> 2) > +#define GPIO_1_8V_E_INT_SENS_0        (0x02C >> 2) > +#define GPIO_1_8V_E_INT_SENS_1        (0x030 >> 2) > +#define GPIO_1_8V_E_INT_SENS_2        (0x034 >> 2) > +#define GPIO_1_8V_E_INT_STATUS        (0x038 >> 2) > +#define GPIO_1_8V_E_RESET_TOLERANT    (0x03C >> 2) > +#define GPIO_1_8V_ABCD_DEBOUNCE_1     (0x040 >> 2) > +#define GPIO_1_8V_ABCD_DEBOUNCE_2     (0x044 >> 2) > +#define GPIO_1_8V_E_DEBOUNCE_1        (0x048 >> 2) > +#define GPIO_1_8V_E_DEBOUNCE_2        (0x04C >> 2) > +#define GPIO_1_8V_DEBOUNCE_TIME_1     (0x050 >> 2) > +#define GPIO_1_8V_DEBOUNCE_TIME_2     (0x054 >> 2) > +#define GPIO_1_8V_DEBOUNCE_TIME_3     (0x058 >> 2) > +#define GPIO_1_8V_ABCD_COMMAND_SRC_0  (0x060 >> 2) > +#define GPIO_1_8V_ABCD_COMMAND_SRC_1  (0x064 >> 2) > +#define GPIO_1_8V_E_COMMAND_SRC_0     (0x068 >> 2) > +#define GPIO_1_8V_E_COMMAND_SRC_1     (0x06C >> 2) > +#define GPIO_1_8V_ABCD_DATA_READ      (0x0C0 >> 2) > +#define GPIO_1_8V_E_DATA_READ         (0x0C4 >> 2) > +#define GPIO_1_8V_ABCD_INPUT_MASK     (0x1D0 >> 2) > +#define GPIO_1_8V_E_INPUT_MASK        (0x1D4 >> 2) > +#define GPIO_1_8V_MEM_SIZE            0x1D8 > +#define GPIO_1_8V_REG_ARRAY_SIZE      (GPIO_1_8V_MEM_SIZE >> 2) >   >  static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, > int gpio) >  {