From: Richard Henderson <richard.henderson@linaro.org>
To: Rebecca Cran <rebecca@nuviainc.com>,
qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU
Date: Mon, 15 Feb 2021 16:20:16 -0800 [thread overview]
Message-ID: <d7aa2e3f-f2b0-eaf7-d1c7-48c211462c45@linaro.org> (raw)
In-Reply-To: <20210215215819.1142-3-rebecca@nuviainc.com>
On 2/15/21 1:58 PM, Rebecca Cran wrote:
> Set ID_AA64PFR1_EL1.SSBS to 2 and ID_PFR2.SSBS to 1.
>
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
> ---
> target/arm/cpu64.c | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-02-16 0:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-15 21:58 [PATCH 0/3] target/arm: Add support for FEAT_SSBS Rebecca Cran
2021-02-15 21:58 ` [PATCH 1/3] target/arm: Add support for FEAT_SSBS, Speculative Store Bypass Safe Rebecca Cran
2021-02-16 0:19 ` Richard Henderson
2021-02-16 2:15 ` Rebecca Cran
2021-02-15 21:58 ` [PATCH 2/3] target/arm: Enable FEAT_SSBS for "max" AARCH64 CPU Rebecca Cran
2021-02-16 0:20 ` Richard Henderson [this message]
2021-02-15 21:58 ` [PATCH 3/3] target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPU Rebecca Cran
2021-02-16 0:20 ` Richard Henderson
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