From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CABE7C432BE for ; Wed, 1 Sep 2021 16:22:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D84460F90 for ; Wed, 1 Sep 2021 16:22:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4D84460F90 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:40688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mLT0S-0005MD-DY for qemu-devel@archiver.kernel.org; Wed, 01 Sep 2021 12:22:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35198) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLSxz-0002RN-8W; Wed, 01 Sep 2021 12:19:59 -0400 Received: from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]:56901) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mLSxv-0003mJ-Dp; Wed, 01 Sep 2021 12:19:58 -0400 Received: from mxplan5.mail.ovh.net (unknown [10.108.16.128]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id F272BBBF04D0; Wed, 1 Sep 2021 18:19:50 +0200 (CEST) Received: from kaod.org (37.59.142.97) by DAG4EX1.mxp5.local (172.16.2.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.14; Wed, 1 Sep 2021 18:19:50 +0200 Authentication-Results: garm.ovh; auth=pass (GARM-97G00222381ebb-9fb0-4881-aac4-995c390bc6ca, 5EBA00A5E723AF1D17FBD8632F6684B6834AEADC) smtp.auth=clg@kaod.org X-OVh-ClientIp: 82.64.250.170 Subject: Re: [PATCH v2 1/1] hw/arm/aspeed: Allow machine to set UART default To: References: <20210901153615.2746885-1-pdel@fb.com> <20210901153615.2746885-2-pdel@fb.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: Date: Wed, 1 Sep 2021 18:19:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210901153615.2746885-2-pdel@fb.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-Originating-IP: [37.59.142.97] X-ClientProxiedBy: DAG6EX1.mxp5.local (172.16.2.51) To DAG4EX1.mxp5.local (172.16.2.31) X-Ovh-Tracer-GUID: e5bcebe1-9804-4ad1-b872-bc48116734e6 X-Ovh-Tracer-Id: 12116371847884540780 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: 0 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedvtddruddvfedgleelucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucenucfjughrpefuvfhfhffkffgfgggjtgfgihesthekredttdefjeenucfhrhhomhepveorughrihgtpgfnvggpifhorghtvghruceotghlgheskhgrohgurdhorhhgqeenucggtffrrghtthgvrhhnpeejkeduueduveelgeduueegkeelffevledujeetffeivdelvdfgkeeufeduheehfeenucfkpheptddrtddrtddrtddpfeejrdehledrudegvddrleejnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmohguvgepshhmthhpqdhouhhtpdhhvghlohepmhigphhlrghnhedrmhgrihhlrdhovhhhrdhnvghtpdhinhgvtheptddrtddrtddrtddpmhgrihhlfhhrohhmpegtlhhgsehkrghougdrohhrghdprhgtphhtthhopehpuggvlhesfhgsrdgtohhm Received-SPF: pass client-ip=178.32.125.2; envelope-from=clg@kaod.org; helo=smtpout1.mo529.mail-out.ovh.net X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-1.029, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, andrew@aj.id.au, f4bug@amsat.org, qemu-devel@nongnu.org, patrick@stwcx.xyz, qemu-arm@nongnu.org, joel@jms.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/1/21 5:36 PM, pdel@fb.com wrote: > From: Peter Delevoryas > > When you run QEMU with an Aspeed machine and a single serial device > using stdio like this: > > qemu -machine ast2600-evb -drive ... -serial stdio > > The guest OS can read and write to the UART5 registers at 0x1E784000 and > it will receive from stdin and write to stdout. The Aspeed SoC's have a > lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on > the board design, may be using any of them as the serial console. (See > "stdout-path" in a DTS to check which one is chosen). > > Most boards, including all of those currently defined in > hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds > some flexibility for different boards without requiring users to change > their command-line invocation of QEMU. > > I tested this doesn't break existing code by booting an AST2500 OpenBMC > image and an AST2600 OpenBMC image, each using UART5 as the console. > > Then I tested switching the default to UART1 and booting an AST2600 > OpenBMC image that uses UART1, and that worked too. > > Signed-off-by: Peter Delevoryas One comment, any how Reviewed-by: Cédric Le Goater > --- > hw/arm/aspeed.c | 3 +++ > hw/arm/aspeed_ast2600.c | 8 ++++---- > hw/arm/aspeed_soc.c | 9 ++++++--- > include/hw/arm/aspeed.h | 1 + > include/hw/arm/aspeed_soc.h | 1 + > 5 files changed, 15 insertions(+), 7 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 9d43e26c51..a81e90c539 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -350,6 +350,8 @@ static void aspeed_machine_init(MachineState *machine) > object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", > ASPEED_SCU_PROT_KEY, &error_abort); > } > + qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default", > + amc->uart_default); > qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); > > memory_region_add_subregion(get_system_memory(), > @@ -804,6 +806,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) > mc->no_parallel = 1; > mc->default_ram_id = "ram"; > amc->macs_mask = ASPEED_MAC0_ON; > + amc->uart_default = ASPEED_DEV_UART5; > > aspeed_machine_class_props_init(oc); > } > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index e3013128c6..b07fcf10a0 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -322,10 +322,10 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); > } > > - /* UART - attach an 8250 to the IO space as our UART5 */ > - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, > - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), > - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); > + /* UART - attach an 8250 to the IO space as our UART */ > + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, > + aspeed_soc_get_irq(s, s->uart_default), 38400, > + serial_hd(0), DEVICE_LITTLE_ENDIAN); > > /* I2C */ > object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), > diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c > index 3ad6c56fa9..09c0f83710 100644 > --- a/hw/arm/aspeed_soc.c > +++ b/hw/arm/aspeed_soc.c > @@ -287,9 +287,9 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) > sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); > } > > - /* UART - attach an 8250 to the IO space as our UART5 */ > - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, > - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), 38400, > + /* UART - attach an 8250 to the IO space as our UART */ > + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, > + aspeed_soc_get_irq(s, s->uart_default), 38400, > serial_hd(0), DEVICE_LITTLE_ENDIAN); > > /* I2C */ > @@ -439,6 +439,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) > static Property aspeed_soc_properties[] = { > DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, > MemoryRegion *), > + DEFINE_PROP_UINT32("uart-default", AspeedSoCState, uart_default, > + ASPEED_DEV_UART5), > DEFINE_PROP_END_OF_LIST(), > }; > > @@ -449,6 +451,7 @@ static void aspeed_soc_class_init(ObjectClass *oc, void *data) > dc->realize = aspeed_soc_realize; > /* Reason: Uses serial_hds and nd_table in realize() directly */ > dc->user_creatable = false; > + Unneeded change, Thanks, C. > device_class_set_props(dc, aspeed_soc_properties); > } > > diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h > index c9747b15fc..cbeacb214c 100644 > --- a/include/hw/arm/aspeed.h > +++ b/include/hw/arm/aspeed.h > @@ -38,6 +38,7 @@ struct AspeedMachineClass { > uint32_t num_cs; > uint32_t macs_mask; > void (*i2c_init)(AspeedMachineState *bmc); > + uint32_t uart_default; > }; > > > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h > index d9161d26d6..87d76c9259 100644 > --- a/include/hw/arm/aspeed_soc.h > +++ b/include/hw/arm/aspeed_soc.h > @@ -65,6 +65,7 @@ struct AspeedSoCState { > AspeedSDHCIState sdhci; > AspeedSDHCIState emmc; > AspeedLPCState lpc; > + uint32_t uart_default; > }; > > #define TYPE_ASPEED_SOC "aspeed-soc" >